ic cell library
Std cell libraries are the basic building block of any advance digital IC, they contain all the combinational & sequential digital & mixed signal cells which will be used for the creation of SOC or ASIC. These cells will be arranged & connected in an orderly & meaning ful pattern by using synthesis tools such as DC or RTL compiler, later on these cells along with other hard & soft marcos are used to create complete SOC. Normally people term .lib as Std cell but they are wrong bc/s Std lib contains gds2, lef, (timing, power area & cap info of cells in .lib syntax), milkyway data base (FRAM, CEL etc.), cdl & RC-info in extracted netlist, noise info in celtic or ccsn formatt, voltage storm views etc. these all views are used at different stages of ASIC design by different EDA tools....
Now PDK its definition varies from company to company what I know is PDK (Process Development Kit) contains info about the process for which the SOC or ASIC is been targetted, they are been even used to create even Std cells, Memories, I/O's & Analog portion typically they contains DRC, DFM, Antenna, LVS & extraction rule decks, along with SPICE models which are used during simulations. All the DRC & DFM info is been used to create P-cells (Cadence nomenclature) which are used in cadence icfb