Thauer
Newbie
I want to design an integrated H-Bridge circuit to drive a load with 100 mA at maximum. To do so, i think that i need to determine the maximum allowed power loss per area to calculate the minimum transistor dimensions.
However, I can not find a value like that in my PDK documentation for the standard transistor. For the metal layer I have found a maximum current density per width. Therefore, my question is whether I am looking for the wrong value and if so, what value/values need to be considered for sizing an integrated power resistor for such a low current.
However, I can not find a value like that in my PDK documentation for the standard transistor. For the metal layer I have found a maximum current density per width. Therefore, my question is whether I am looking for the wrong value and if so, what value/values need to be considered for sizing an integrated power resistor for such a low current.