sun_ray
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If the requirement of the PCS design of a PHY is 1G bits per second with the interface width to be 6 bits, the operating clock frequency for the PCS is taken as
1G/6 = 166.66 MHz. Is this calculation on the basis of RX path receiving data from media at 1G bits per second and sending the parallel data to MAC?
But the data is sent from PCS to PMA at 166.66 MHz in the transmit path, and the PMA receives this data from PCS at a frequency lesser than 166.66 MHz. How then the PMA exit the data at 1G bits per second then?
1G/6 = 166.66 MHz. Is this calculation on the basis of RX path receiving data from media at 1G bits per second and sending the parallel data to MAC?
But the data is sent from PCS to PMA at 166.66 MHz in the transmit path, and the PMA receives this data from PCS at a frequency lesser than 166.66 MHz. How then the PMA exit the data at 1G bits per second then?