PCIe lane reversal, P/N reversal, lane swapping, etc support. Also length matching!

[uoficowboy]

I understand PCIe can sometimes be quite flexible in terms of lane usage. But where I get confused is what flexibilities always exist vs which only sometimes exist. This is my understanding:

• You can swap P/N within a pair. There is no requirement that if you swap RX0 on a x4 interface that you also swap RX1-RX3 or TX0. I believe this is always supported (even for gen 1?)
• You can reverse the order of lanes. So on a x4 you can connect RX0 to RX3, RX 1 to RX2, and so on. I believe this is typically supported but not always? Is this only supported in later generations? If you swap RX you don't need to swap TX? (this one I'm not very sure about)
• I've heard some chips support arbitrary lane swapping (so on a x4 connect RX0 to RX2, RX1 to RX3, etc). I believe this is not part of the standard and is a fairly rare feature.

Is that all accurate?

Further - I've seen conflicting information on length matching. I believe:

• P to N have to be matched within a pair. I've seen 5 mils given as a typical target for gen 1 - gen 4
• Intra pair may may need to be matched (as in, RX0 to RX1). I see some docs that suggest 550 mils while others suggest there is no need for matching.
• RX to TX have no matching requirements, I believe (as in, RX0 to TX0).
• CLK has no length matching requirement besides P to N (typically target 5 mils). But for example if your root complex and endpoint are both being driven by the same clock fanout buffer - there is no need to match length of traces there besides P to N.

Can you please point out any mistakes in the above? I'm not working on a specific problem here just want to make sure my understanding is good. Thank you!