PCIe Enumeration and BAR Configuration of Rootcomplex and End point

Hi,

Please Help me in understanding enumeration related to PCIe.

1] During Enumeration Host/Driver reads BAR's of Root Complex & End Point using api's and configure the BAR's as per request.
Root Complex will only read BAR values of End point using CFGRD. It wont configure them by sending CFGWR TLP.
- Please Correct If I am wrong.


2] After Link up RC will read EP BAR's and Knows BAR value of Endpoint to communicate further.
- Please Correct If I am wrong.

3] How End point knows the Root complex BAR Configuration values? Through host driven api's?
- Please explain

4] In One Scenario Root complex is BFM and End point is DUT. In DUT only BAR0 32-bit is configured.But After Link up
RC BFM is reading remaining BAR's 1/2/3/4/5 along with BAR0 and getting some value. Is it Expected behavior? Please explain
little bit if you know.
In Real Hardware at this situation RC will knows EP configuration and read only BAR0 by sending CFGRD. Is my understanding
Correct?

Regards
Vinay