Microstrip on the outer layer shares the relative dielectric constant of the PCB and air on the other side. Stripline has the PCB dielectric on both sides.
Because of the influence of air, microstrip uses a lower
effective Er, which may be around 80% of Er and only slightly influenced by geometry.
Since stripline is slower, it has a 24% longer wavelength (1/~80%)
ref
Saturn PCB Toolkit
Max conductor length is often quoted from 10 to 20% of wavelength and depends if the load is not matched then two path lengths are important.
Thus 1/15th of the wavelength of the signal is recommended according to IPC-2251.
Your link recommends the delay line should not exceed 1/2 of the risetime (10~90%)
If I make the delay equal to the rise time, the signal starts to ring when loaded by a CMOS gate capacitance but looks damped when loaded near Zo.
My Sig Gen assumes high-speed CMOS with 1ns rise time. with Zout = 22~23 ohms
Using 10 MHz with d.f = 10% for a 10 ns pulse width and BW = 0.34/10ns = 34 MHz
View attachment 192964
This would be acceptable for B. and overshoot would be clamped better than shown by CMOS ESD/SCR protection.
1nF 1ohm to simulate CMOS Miller capacitance amplified with 1ns = Tr
If too long, probes will ring from ground clip inductance and capture similar ringing due to probe capacitance and excess gnd length > 1cm.
Now using 100 MHz 20% = 2 ns PW on 1 ns delay line is the limit of length for unterminated lines on CMOS. The number of gates will limit the BW and risetime on the CMOS driver.
View attachment 192965