[SOLVED] PCB trace critical length...

[sapphire_2010]

How to calculate critical trace length on a PCB, in both time and frequency domain method? Is there any calculator available?
I found below link as a reference, but wondering if the formula remain same whether my trace is in outer or inner layer?

https://www.ema-eda.com/ema-resources/blog/when-is-my-printed-circuit-board-considered-high-speed/

 

[D.A.(Tony)Stewart]

Microstrip on the outer layer shares the relative dielectric constant of the PCB and air on the other side. Stripline has the PCB dielectric on both sides.

Because of the influence of air, microstrip uses a lower effective Er, which may be around 80% of Er and only slightly influenced by geometry. Since stripline is slower, it has a 24% longer wavelength (1/~80%)


ref Saturn PCB Toolkit


Max conductor length is often quoted from 10 to 20% of wavelength and depends if the load is not matched then two path lengths are important.

Thus 1/15th of the wavelength of the signal is recommended according to IPC-2251.

Your link recommends the delay line should not exceed 1/2 of the risetime (10~90%)

If I make the delay equal to the rise time, the signal starts to ring when loaded by a CMOS gate capacitance but looks damped when loaded near Zo.

My Sig Gen assumes high-speed CMOS with 1ns rise time. with Zout = 22~23 ohms
Using 10 MHz with d.f = 10% for a 10 ns pulse width and BW = 0.34/10ns = 34 MHz

This would be acceptable for B. and overshoot would be clamped better than shown by CMOS ESD/SCR protection.

1nF 1ohm to simulate CMOS Miller capacitance amplified with 1ns = Tr

If too long, probes will ring from ground clip inductance and capture similar ringing due to probe capacitance and excess gnd length > 1cm.

Now using 100 MHz 20% = 2 ns PW on 1 ns delay line is the limit of length for unterminated lines on CMOS. The number of gates will limit the BW and risetime on the CMOS driver.

https://tinyurl.com/234rtcfa

 

[sapphire_2010]

Microstrip on the outer layer shares the relative dielectric constant of the PCB and air on the other side. Stripline has the PCB dielectric on both sides.

Because of the influence of air, microstrip uses a lower effective Er, which may be around 80% of Er and only slightly influenced by geometry. Since stripline is slower, it has a 24% longer wavelength (1/~80%)


ref Saturn PCB Toolkit


Max conductor length is often quoted from 10 to 20% of wavelength and depends if the load is not matched then two path lengths are important.

Thus 1/15th of the wavelength of the signal is recommended according to IPC-2251.

Your link recommends the delay line should not exceed 1/2 of the risetime (10~90%)

If I make the delay equal to the rise time, the signal starts to ring when loaded by a CMOS gate capacitance but looks damped when loaded near Zo.

My Sig Gen assumes high-speed CMOS with 1ns rise time. with Zout = 22~23 ohms
Using 10 MHz with d.f = 10% for a 10 ns pulse width and BW = 0.34/10ns = 34 MHz

View attachment 192964

This would be acceptable for B. and overshoot would be clamped better than shown by CMOS ESD/SCR protection.

1nF 1ohm to simulate CMOS Miller capacitance amplified with 1ns = Tr

If too long, probes will ring from ground clip inductance and capture similar ringing due to probe capacitance and excess gnd length > 1cm.

Now using 100 MHz 20% = 2 ns PW on 1 ns delay line is the limit of length for unterminated lines on CMOS. The number of gates will limit the BW and risetime on the CMOS driver.

View attachment 192965

https://tinyurl.com/234rtcfa

Hi Tony,
Thanks for your detailed explanation.
I agree that outer layer share air and PCB dielectric at the same time, so there will be an effective Er (approx ~ 0.64*Er + 0.36). Regarding Saturn toolkit, i think it is good to kick start. But i am confused on what "Sr" Factor should be used .....or what lambda factor should be more appropriate, as there are multiple choices? any suggestions?

 

[D.A.(Tony)Stewart]

Hi Tony,
Thanks for your detailed explanation.
I agree that outer layer share air and PCB dielectric at the same time, so there will be an effective Er (approx ~ 0.64*Er + 0.36). Regarding Saturn toolkit, i think it is good to kick start. But i am confused on what "Sr" Factor should be used .....or what lambda factor should be more appropriate, as there are multiple choices? any suggestions?

These are two criteria (time and wavelength)

1. Sr=Slew Rate method means choose path length by ratio of rise time which affects residual amplitude error from reflection.

Note Sr=1.0 with Tr=1ns and Td=1ns

In my method with a mismatched load I used Sr =1ns/1ns = 1.0 A shorter delay is recommended as you can see the noise for Sr<0.5
Review my answer again

The other method correlates due to the conversion of rise time to the shortest wavelength.

 

[sapphire_2010]

These are two criteria (time and wavelength)

1. Sr=Slew Rate method means choose path length by ratio of rise time which affects residual amplitude error from reflection.

Note Sr=1.0 with Tr=1ns and Td=1ns
View attachment 193008
In my method with a mismatched load I used Sr =1ns/1ns = 1.0 A shorter delay is recommended as you can see the noise for Sr<0.5
Review my answer again

The other method correlates due to the conversion of rise time to the shortest wavelength.

Thanks for your help Tony, I got your point.