PCB throughhole Via looks like connecting to every layer.

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shemo

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I have this via structure,

It looks like its throughhole but I don't see any clearance/isolation area with other layers.

Is that means it's touching and connecting to every single layers?

It doesn't make sense.

If it's a via to ground then its touching the ground plane and clearance/isolates with other layers.

From the picture it looks like it touch every single layer.
 

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Hello. I think all the via structure are the same , and that's why they are called Through Holes.

See. the red dot is the vias. The green area are copper.
 

I think u called out in DRC mode. so u got clearance in all other nets

basically two modes present, please check
 

Why wouldn't it make sense? If you use the vias to stitch polygons together with a ground plane, for example, this makes perfect sense.

If the via's are assigned to the proper electrical net then the problem should solve itself if you repour your polygons, fills and planes.
 

SO the copper through hole via touching inner layer SIG1 and SIG2 is OK?

I don't think so,
 

It depends on the clearance on each layer. If you have an annular ring on the inner layers specified without a clearance around it, you may have a problem. From your 3D window there is no annular rings on the inner layers. So then it is depending on the clearance around the via.

You will of course have a connection, if the net in question is routed on an inner layer.

If you are in doubt, generate a set of gerber files and see what you get in a gerber viewer. then you can see if your specification is correct. A run of the DRC should also mark this as an error if it is in the test matrix.
 

Your anti pad clearance seems to be set to zero! maybe this is the problem...
 

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