PCB layout requirement for 10 Gbps

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engr_joni_ee

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Hi,
The Xilinx Ultrascale MPSoC have GTH transceivers. There are some development boards with SFP+ connector which can support up to 10 Gbps for example ZCU102 and ZCU106. There are only two differential pair between PL and SFP+ connector, one for Tx and other for Rx. Each way is 10 Gbps. Which signaling on these differential pairs, LVDS or some other ? If LVDS then how a digital signal with clock frequency 5 GHz is routed on FR4 PCB ? Isn't is too high speed signal for LVDS routing on FR4 ?
 

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Dear Friend,


Dear Friend,

See the standard "JESD204C" also.

Regards,
PCB Designers.
 

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Most questions are answered in the "LVDS owners manual", second paper in post #2. I also presume that the sayed dev boards are using some kind of FR4, most likely with tighter spec like Nelco 4000-6 discussed in the TI paper.

An important parameter, not yet mentioned is length. Transmission lines have a constant attenuation per length unit. SFP+ differential pairs on a PCIe board are 2-3, maximal 4 inch long. That's well possible with "good" FR4 and proper routing.
 

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I just discover that Xilinx Ultrascale MPSoC's GTH transceivers use a high-speed serial interface called CML. This is called Current Mode Logic, not LVDS. CML is suitable for high-speed data transmission, like 10 Gbps which is beyond LVDS can handle.

What are the PCB design requirement for routing CML signals on FR4 ? What are impedance and trance length requirement ?

And is it possible to simulate CML interface in HpyerLynx ? I know we can simulate a LVDS differential net in HyperLynx but how it goes with CML ?
 
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