PCB layout feedback (SMPS)

[Fever]

Hi,

I'm trying to layout a SMPS that gets 12V, ad outputs 3.3V. The maximal current will not exceed 1 Amp.

I would like to know what you think about this layout, and if there is major or minor issues.

More importantly, I am a bit confused about a line in the datasheet saying "5. Do not allow switching current to flow under the device."
I guess that's exactly what I'm doing and would like to know why it is so important.

Schematic


Top layer


Bottom layer


3D view


Note : Please ignore badly placed designators, they were placed in a hurry.

Thank you very much.

 

[KlausST]

Hi,

I can´t verify the design without datasheet. And for finding the datsheet we need to know the name of the IC.

Schematic issues:
* write the name of the IC in the schematic
* try to follow standard signal flow from left to right. Left side = input, right side = output.
* don´t try to use use the same pin order for the schematic symbol as in the package. Place the pins in a way to make the signal flow more easy and more straight forward.
Here: Left side: VIN, EN, GND. right side: VBST, SW, VFB

Klaus

 

[Fever]

I apologize, I completely for the datasheet. https://www.ti.com/lit/ds/symlink/tps562208.pdf

Yes I get it, I will modify it as soon as possible. The reason why I did draw the schematic like that is that I followed datasheet's schematic. But it's not very conventional indeed.

Thanks

 

[KlausST]

Hi,

I see no big mistakes, besides the "current flow under the device".
There is a risk the voltage/current is beeing coupled to the inside of the device. ...maybe confusing the feedback or clock generation circuit.
--> try to do a redesign


I personally
don´t like the GND plane/area on both sides. It´s no mistake.
Only the capacitor connection to the IC_GND on the TOP may improve input impedance. Then just add a couple of vias close to the capacitors.

Here the "pulse current loop" when switch is ON:


Here the "pulse current loop" when switch is OFF:

Rules of thumb:
* The shorter and the wider the traces the lower the impedance.
* The smaller the enclosed area the lower the EMI

Klaus

 

[Fever]

Thanks !

I see. I tried an other design yesterday, removed the vias for now, and modified it in GIMP because I don't have my CAD software available right now.

Do you think this technique might be better ? SW is not running under device, but goes on bottom layer (We assume there is no ground plane on bottom layer right now). Is it okay to think about manufacturing this style or do I need to redesign it from scratch ?

Here is the picture :



Edit : I fixed a track so had to update image.

Thanks

 

[KlausST]

Hi,

Maybe a misunderstanding.
I did not recommend to remove the GND vias. Now it is worse.
I recommended to remove all the TOP GND except for the connection between IC_GND and input_capacitor_GND. But the vias to GND should be close to the SMD pads.

The switching node still is under the package, but not the load current.
But the ENABLE could be much shorter if you wire it directely from pin5 under the package... and foru sure you need to place the reistor accordingly.

Additionally worse:
befor the GND connection for the feedback resistor was really kevin style, now it is worse, because the complete ripplecurrent of the output capacitors is fed on the same trace.
similar with the voltage feedback wiring.

In short,
now it`s:
Better: the switching path to the inductor
Worse: all other modifications.

Klaus

 

[Fever]

Hey,

I understand the things you pointed out, but I'm still a bit confused about what a Kelvin connection really is in the end.

Anyway I tried to follow as much as possible your advices, I came with this. I think it is a bit better than the first one, and that's for me very close to the limits where I have to redesign everything.

I really appreciate your help.

Note : The vias are as small as possible, and as close as possible to the pins.

Here we go :

 

[KlausST]

Hi,

Kelvin connection of feedback path:
* GND is about perfect now. The point of interest is the GND output connector. Power comes from one side to this pin and the feedback is connected with a seperate trace. (no current flow)
* +Out is not that perfect. Power is fed with one trace to that pin...and the feedback is not connected with a separate trace to the connector. Instead it is connected to the current feeding trace.

The layout is much better now.
Is there a reason why you cut the BOTTOM GND plane?

Klaus

 

[Fever]

Hi,

I think I get what you mean, so I separated the feedback trace from the current feeding trace.

Am I good with this ?




I did'nt fill the bottom layer ground so you could see the bottom layer trace (SW) a bit easier.

Thank you

 

[c_mitra]

What is the role of Q1 here?

 

[KlausST]

Hi,

Now this is a Kelvin connection .

Good job.
Hope you are satisfied with the (electrical) results.

Klaus

Btw:
Your layout now is: input at the left side, output at the right side. This is good for non complex devices. With simple wiring, where no GND star point is needed.
In detail - especially when a load is connected - you may see tiny AC voltage between input_GND and output_GND.
With complex devices you may have several GND wires...sometimes they cause a low impedance external connection between input_GND and output_GND. Now the "tiny AC voltage" may cause serious currents...causing EMI.
Thus I like the input and output connectors to be in close proximity, especially both GND connections.
This enables a good star point wiring.

Klaus

 

[Fever]

Hello,

c_mitra : Q1 is a P-channel mosfet to protect against reverse polarity.

Klaus, thank you for those precisions. I am having a hard time visualizing how I could implement a ground star point in this layout, but I think it is not a big deal anyway for my applications.

So do you think this layout is now good enough to be manufactured ?

Thank you very much.

 

[KlausST]

Hi,

So do you think this layout is now good enough to be manufactured ?

Looks good.

I have not checked things like
* mounting holes
* distance to outline
* texts
* via dimensions
* trace dimensions
* distance clearance
* part dimensions
and so on....

Klaus

 

[Fever]

Hi,

I already verified all the things you pointed out and ran a design rule check with no error.

All the footprints have been verified too, and for the dimensions I don't remember everything except the smallest track is 0.254mm wide, and the connector on the right is a basic 2.54mm 2 holes connector.

I will verify everything a second time, generate gerbers and drill files.

Thank you for you help, I learned quite a lot ! :smile:

 

[treez]

here is my "pcb layout for smps" document...please enjoy to the full!