PCB design layout size

Similar threads

• G

  can we design FPGA?

  • Started by gary36
  • Oct 29, 2024
  • Replies: 18

  PLD, SPLD, GAL, CPLD, FPGA Design
• E

  Is there anything that converts verilog to resistor, capacitor level design?

  • Started by electronicslab
  • Oct 27, 2024
  • Replies: 1

  PLD, SPLD, GAL, CPLD, FPGA Design
• K

  [Merged] Why it cannot be read by Design Compiler? (reading takes too long/stuck)

  • Started by KYLI0418
  • Nov 5, 2024
  • Replies: 12

  PLD, SPLD, GAL, CPLD, FPGA Design
• A

  How to extract input/reg size in Verilog?

  • Started by adamira
  • Mar 15, 2023
  • Replies: 7

  PLD, SPLD, GAL, CPLD, FPGA Design
• E

  Data bits swap in PCB layout of SDRAM DDRL3L and length matching

  • Started by engr_joni_ee
  • Apr 22, 2022
  • Replies: 4

  PLD, SPLD, GAL, CPLD, FPGA Design