kewe
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I have recently been tasked with designing PCB's for Ethernet Connectors.
This can either be a PCB internally within the connector, or a PCB where the RJ45 Jack is mounted.
Most PCB's are Double sided and the internal version has no GND.
In both cases, it seems that using interdigitated capacitors i.e. finger tracks between certain pins can help compensate for NEXT and FEXT coming from the Connectors.
I noticed a thread raised a while back that touched on this subject, but not much info:-
https://www.edaboard.com/threads/110547/
Does anybody have any knowledge of how to make these calculations for the compensation on the PCB?
There seems to be a lot of Patents out there for this type of technology :-(
Regards,
This can either be a PCB internally within the connector, or a PCB where the RJ45 Jack is mounted.
Most PCB's are Double sided and the internal version has no GND.
In both cases, it seems that using interdigitated capacitors i.e. finger tracks between certain pins can help compensate for NEXT and FEXT coming from the Connectors.
I noticed a thread raised a while back that touched on this subject, but not much info:-
https://www.edaboard.com/threads/110547/
Does anybody have any knowledge of how to make these calculations for the compensation on the PCB?
There seems to be a lot of Patents out there for this type of technology :-(
Regards,