PC Oscilloscope redesign: the minimum size of FIFO?

[CMOS]

design pc oscilloscope

I want to modify the design of PC base oscilloscope given here **broken link removed**

But the bandwidth is limited to 500kHz due to the FT245 USB data transfer limitation of 1MB/s. I want to increase the bandwidth to something useful like say 20MHz using high speed ADC (40MSPS, 8-bit) and FIFO buffer.

Now the problem is that how do I calculate the FIFO buffer depth to convert ADC data rate of 40MB/s to USB data rate of 1MB/s. What will be the minimum size of FIFO required?

 

[CMOS]

high speed adc fifo oscilloscopes

No solutions ??

 

[jhbbunch]

oscilloscope ft2232

I don't see why USB would be a bottleneck. You would have the ADC fire the data out to a memory chip. Obviously at the EOC (end of conversion signal) you would have circuitry (a counter) that would increment the memory address by one and you would have circuitry (a comparator) that would signal the end of frame (end of data collection). Then probably a micro would go through the memory, gathering it up into packages and firing it over the USB to the computer where it is presented in some kind of graphic format. There is no inherent limitation to this kind of interface in terms of bandwidth. A screen only refreshed 50 - 90 times a seconds. The human eye can't discern more that about a 30 fps refresh rate. If you want continous streams of data that would be another thing but who datalogs in the Megahertz range?

 

[CMOS]

Re: PC Oscilloscope Redesign

USB bandwidth is not a problem but the FTDI chip FT245 can upload data to USB port at 1MB/s and I feel sending data continuously to PC will be a better option rather than sending it intermittently.

 

[BeeBop]

Re: PC Oscilloscope Redesign

Have you come across the bitscope site? I think it may offer you a few ideas on bandwidth, and other things. Here, have a look:https://www.bitscope.com/
Hope this helps some!
regards,
Robert

 

[JohnJ]

Re: PC Oscilloscope Redesign

I've been working on a design for a DSO myself for a while (who hasn't?) I found these FIFOs from TI. They have selectable 9 or 18 bit wide input and output (can convert from one to the other) and several depths up to 128k x 9. The read and write are totally independent (speed) from each other. Best yet, they will work up to 166MHz :!: When you only need, lets say 50MHz that makes timing REAL easy. The extra 1 or 2 bits are meant for interfacing busses with parity bits.
They have programmable almost-full and almost-empty flags which means you can set your number of samples before you go to sample the signal and stop automatically. You can also use ADC's with up to 16bits and still send the data thru in 8 bit pieces.
Now you can sample up to 166MSPS and read out to the USB chip at whatever speed you want. A quick review of the controls looks to me that you can directly interface the FIFO to the USB chip with little or no external logic.

Even though they are 3.3V parts, they are 5V input tolerant and their outputs meet the minimum input high for most 5V parts.

The datasheet can be intimidating if you are new to this, but I just cross out the sections on features I'm not going to use.
Here's the link:
**broken link removed**

TI is pretty good with samples, so they shouldn't be to hard to get. They do list at ~$20 US 1000units. TI "limits" you to something like 5 (free)samples PER WEEK. Search around TI's site for other FIFOs that may be cheaper if you can't get samples from them.

I was looking at using seperate SRAM and generating addresses and stuff with a fast FPLD but this reduced the complexity of my design enormously I can now use all that logic to peak detect, average, or whatever. Eliminating all those address lines switching on the board should also reduce the switching noise that likes to get into the input.

My design is looking at 200MSPS but I sometimes design PCBoards and have access to several 6 and 8 GHz (20ps/sample) Tektronics DSO's here at work to debug my designs. (Yes, sometimes we don't have to die to go to heaven )

 

[CMOS]

Re: PC Oscilloscope Redesign

I've been working on a design for a DSO myself for a while (who hasn't?) I found these FIFOs from TI. They have selectable 9 or 18 bit wide input and output (can convert from one to the other) and several depths up to 128k x 9. The read and write are totally independent (speed) from each other. Best yet, they will work up to 166MHz :!: When you only need, lets say 50MHz that makes timing REAL easy. The extra 1 or 2 bits are meant for interfacing busses with parity bits.
They have programmable almost-full and almost-empty flags which means you can set your number of samples before you go to sample the signal and stop automatically. You can also use ADC's with up to 16bits and still send the data thru in 8 bit pieces.
Now you can sample up to 166MSPS and read out to the USB chip at whatever speed you want. A quick review of the controls looks to me that you can directly interface the FIFO to the USB chip with little or no external logic.

Even though they are 3.3V parts, they are 5V input tolerant and their outputs meet the minimum input high for most 5V parts.

The datasheet can be intimidating if you are new to this, but I just cross out the sections on features I'm not going to use.
Here's the link:
**broken link removed**

TI is pretty good with samples, so they shouldn't be to hard to get. They do list at ~$20 US 1000units. TI "limits" you to something like 5 (free)samples PER WEEK. Search around TI's site for other FIFOs that may be cheaper if you can't get samples from them.

I was looking at using seperate SRAM and generating addresses and stuff with a fast FPLD but this reduced the complexity of my design enormously I can now use all that logic to peak detect, average, or whatever. Eliminating all those address lines switching on the board should also reduce the switching noise that likes to get into the input.

My design is looking at 200MSPS but I sometimes design PCBoards and have access to several 6 and 8 GHz (20ps/sample) Tektronics DSO's here at work to debug my designs. (Yes, sometimes we don't have to die to go to heaven )

Can you share your design?

 

[JohnJ]

Re: PC Oscilloscope Redesign

I will get at least a block diagram this coming weekend! I have picked all the chips but haven't put the system on paper. Twice now I've started, and had my PC crash (unrelated).

What about your clock generator? As you have heard, sampling clock jitter will show up as noise in the output. A suggestion is Lattice Semiconductor's IspClock5610. It appears to have pretty good jitter specs, has all kinds of input and output types. (LVTTL, LVCMOS, LVPECL, SSTL, HSTL).

Does anyone know of a better one?

 

[fms]

Re: PC Oscilloscope Redesign

i've been searching the net for pc based osc for quite some time now. but i still think bitscope is still the best. mayb u can share the 2 programs when ur done with the project? thanks in advance.