Pause and Exit States in JTAG FSM

[mvkarthik]

Hi,

I am new to DFT and wanted to know what is the relevance of Pause and Exit1,2 states in JTAG FSM. Can someone explain it / post a link that I can refer to ?

 

[FvM]

Don't expect exhausting answers. The purpose of PAUSE-DR and PAUSE-IR isn't clearly explained even in IEEE 1149.1

I also don't find convincing explanations in literature, rather a paraphrase of the function, e.g.

The reason for entering the Pause state is to temporarily suspend the shifting of data through either the selected data register or instruction register while a required operation, such as refilling a tester memory buffer, is performed.

in: https://www.ti.com/lit/an/ssya002c/ssya002c.pdf

In my view, the state only serves a purpose if tester hardware uses TCK for operations outside the DUT. This is hardly the case in recent JTAG interfaces, there are even errata reports for certain chips that causes errors when using PAUSE-xx states. I think it's just legacy. EXITx-xx states are only needed to support PAUSE.