Actually the verilog version will work as shown below, because "shift"
will start with all 'x', after eight zeros are shifted in the out will go HI
and stay HI forever.
The gate version will not work because the "shift" may contain any
value from 0 to 255. The result will be correct only when the least signifiant bit is HI.
module fsm (in, out );
input in;
output out;
reg out;
reg[7:0] shift;
always @ ( negedge in ) begin
shift[7:0] = {shift[6:0], 1'b0};
end
always @ (shift) begin
if (shift== 0)
out = 1;
else out = 0 ;
end
endmodule
Regards,
Shell3