pathing difficulties in common centroid structure

[sunjiao3]

Hi, friends.
I am trying to layout a pair of differential nmos, which are used in high-speed amplifier. The inputs terminals are their gate. And their layout are like follows:
A1/2 | A2/2
--------------------
A2/2 | A1/2
The difficulty is, to protect each of the input signal, in1 and in2 can not be overlapped, while, in common centroid structure, overlapping seems unavoidable. Before, during layouting some other ckt work in low frequencies, I also encountered these pathing pathing problems.
So, could anyone give me some suggestion on it ? By the way, any examples layout of common centroid are welcome.
Thank you very much !

 

[franck]

Hi,

What do you exactly mean by high speed?
If you really want your input not crossing you should just not use a common centroid structure.
It's what you usually do in RF applications.

Franck.

 

[sunjiao3]

Thank you, Franck.
Here, the frequency may not be so high___150MHz or so. So, what you mean is that I should choose between match and signal integrity, right? Why we usually didn't use common centroid in RF design? Could you please explain it more clearly?
What's more, in my opinion, common centroid is more important for mos transistors with small sizes than those with big sizes, since the relative mismatch is smaller for the latter. Is it right?
Thank you all again.

 

[cretu]

Thank you, Franck.
Here, the frequency may not be so high___150MHz or so. So, what you mean is that I should choose between match and signal integrity, right? Why we usually didn't use common centroid in RF design? Could you please explain it more clearly?
What's more, in my opinion, common centroid is more important for mos transistors with small sizes than those with big sizes, since the relative mismatch is smaller for the latter. Is it right?
Thank you all again.

Hi sunjiao

the big size transistors have a better matching due to the fact that the mismatch error is proportional with 1/(WL)sqrt (the biger WL the smaller the error). On the other hand common centroid is good to use(for smallsize or big size transistors) even at frequencies greater than 150MHz. The highest frequency I have used such a layout technique was 1.5GHz with very good results.

Common centroid also takes into account the thermal gradients

And something else..if there is a differential input you should not worry that much about a little coupling between the inputs

 

[hebu]

the common centroid layout is with better matching property but hard to route.
I think use inter-digitized layout should be enough.

 

[franck]

Hi,

If it worked at 1.5 GHz, that's great but remember that to optimized a rf path you should route as straight as possible. A common centroid is not the best way to do this. Also for a LNA you should connect your gate both side and again a common centroid is not the best way to do this. In a PA it seems to me very complicated to use such a structure ...
At 150 MHz I think you can use a common centroid structure. But it's really your design which can tell you what to do. If you really worry about crossing or fringing your input, space them by at least 3 time their width and at the cross use 2 metal with the biggest vertical spacing. That will increase your structure but as long as it is a common centroid that doesn't really matter.
Hope it helps,

Franck.

 

[cretu]

Hi Franck

Spacing the two inputs/outputs is good as long as you have enough coupling between them(to make sure that both signals are affected by disturbances the same way). IF we space them too much, the coupling will be weak and you might end up with a pseudo-differential behaviour. At over 5GHz we used 3x, 4x the width of the wire as a max/optimal distance between a diff pair.

And last but not least, in my opinion the most important word is differential..so some coupling is not harming the circuit

PS hebu is right if after that we also have a differential pair/structure... interdigitized structures could do the job. Any diff offset will be transformed in a shift in the common mode voltage

 

[franck]

Hi,

3x time width spacing for differential input pair is fine as long as your lines are not too big which should be the case for an 150 MHz application, via width is enough.
Cretu, are you doing common centroid structure at 5 GHz? Do you speak about circuit as LNA, PA, driver ...? Because if it's the case I'm really interesting in how you are doing your layout. I don't say that it doens't work but you certainly don't have the optimized extraction that you should look for ...
Again at high frequency keep your rf path as straight as possible. This is the best way to do layout at this frequencies.
sunjiao3, if you're design is sensitive to the offset you should use a common centroid structure, if not just do your layout straight and that should be fine.

Franck.

 

[cretu]

Hi,

3x time width spacing for differential input pair is fine as long as your lines are not too big which should be the case for an 150 MHz application, via width is enough.
Cretu, are you doing common centroid structure at 5 GHz? Do you speak about circuit as LNA, PA, driver ...? Because if it's the case I'm really interesting in how you are doing your layout. I don't say that it doens't work but you certainly don't have the optimized extraction that you should look for ...
Again at high frequency keep your rf path as straight as possible. This is the best way to do layout at this frequencies.
sunjiao3, if you're design is sensitive to the offset you should use a common centroid structure, if not just do your layout straight and that should be fine.

Franck.

I did it in the past and usually good matching was required so common centroid was the best choice. With respect to the lines being straight you are right about it. I have to add from experience that sometimes you can't keep the lines straight and you have to use 45 degrees angles. Is very important that both lines have the same number of angles.

The same applies to a pcb board working above or around those frequencies. I had to do my own pcb boards(there was nobody who could provide them at that time) 4-5 years ago when 10G ethernet and other high speed applications where emerging . The killing factor was ,on top of the lines, the connector

regards

 

[sunjiao3]

Thank you all very much.
Still another problem. In this board, I read an opinion some time ago. It suggested that in doing layout of high frequency ckt, tie the 2 ends of the gates. while in differential pairs, gates are the inputs. If I use a kind of technology which has high shell resistence, is it proper for me to alleviate the effects of res by tieing the 2 ends of gates by metal, which will be used as input ends of high frequency signal? If I do so, the output signal, which usually comes out of the drift ends, will cross above the metal connecting the gate ends( the input ends), thus, cap will be induced between input and output.
So, could you please give me some suggestion, and clarify me on the variation of voltage along the channel width.
Thank you all again !

 

[yorande]

Hi, I don't quite understand.
why should we tie the 2 ends of the gates??

 

[franck]

Hi,

I talked about straight rf path and not physical straight lines. And straight doesn't mean orthogonal. I'm quite aware of 45 angle ...
5 years ago I was already doing rf layout and we never used a common centroid structure in rf circuit in all the company I worked with. I saw that before of course and just by changing the layout to a simple topology the performance wa better.
Even if you always have to take care of matching, there is a lot of place in an rf chip where you need to have very good routing as simple as possible than to do the best matching you can. Again if you want to kill a PA, just do a common centroid structure on the diff pair. That will also increase your layout area by a huge fatcor. By the way I never see that.
I can't talk about PCB but I think that is not really the point of this topic.
Anyway that's really interesting how the method apply for layout are just the opposite sometimes ...
Some doesn't work, some work and some are optimized. The last should be the ultimate goal for me but I know that in some application and companies that's not the case.

Cheers,
Franck

Added after 16 minutes:

you should tie both ends of gates to reduce your access resistance.
After source and drain connection depends on the area of your device.
On small device connect the source on one of the ends and connect the drain with the top metal over the mos. For those who don't agree with this kind of routing just connect the drain on the other end.
For big devices you should use a unit cell containing 4 small devices flip 2 by 2 with gate contact on both ends. Share the drain horizontaly with the n-1 top metal. Route the source on top and bottom of your cell and route the gate under. Don't route the gate under the drain stripe. By instanciating this unit with the correct number of row and column you have your device that you can connect with 2 method. top metal over the mos for both source and drain. Or split your array in 2 and route the drain in the middle and source both side. I'm sure there is a lot more method. That jsut what I use to do.

Cheers,
Franck.

 

[sunjiao3]

Thank you very much, Franck.
But, as for the method to tie both ends of the gate, could you please make it more clearly? Maybe a simple graph is better. Thank you again!

 

[yorande]

I think that means when a gate is long, then we tie its both ends..
not tie the ends of two gates.

But I have new questions now,

why "Don't route the gate under the drain stripe."?

And I guess MOSes for PAs are very big, if they can't use common centroid or interdigitized structure then the performances of them could vary much. How could people make products with them?

And why could we end up with a pseudo-differential behaviour just because of the layout?

Thanks!!