path exercised by test bench vectors in a gate-level or RTL design

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tariq786

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Hi guys,


if i run test bench vectors through a design, how can i see and list all the paths exercised by the input vectors in a gate-level design or RTL design?
 

any one ???

Its strange that no body replied.
 

Hi i think you need the coverage report which will throw throw light on the paths being unsensitized.
 
there should be other ways to get this information besides coverage report. Who can help me with that?
 

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