path exercised by test bench vectors in a gate-level or RTL design

[tariq786]

Hi guys,


if i run test bench vectors through a design, how can i see and list all the paths exercised by the input vectors in a gate-level design or RTL design?

 

[tariq786]

any one ???

Its strange that no body replied.

 

[sakthikumaran87]

Hi i think you need the coverage report which will throw throw light on the paths being unsensitized.

 

[tariq786]

there should be other ways to get this information besides coverage report. Who can help me with that?