Partial Reconfiguration and Scrubbing

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msdarvishi

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Hello everybody,

I am looking for some information for mitigation techniques in Xilinx Virtex FPGAs and I got confused with the following concepts:

- What is the difference between partial reconfiguration and scrubbing? Are they the same?
- Are Module-based and Difference-based partial reconfiguration differ from Scrubbing techniques (Blind and Predictive)?
- Readback technique and its relation to partial reconfiguration.

Can anybody clarify them to me?

Thanks,
 

Partial reconfiguration is when you change the functionality of the FPGA on the fly under YOUR control, as a function of your design.

Scrubbing is a function, where you attempt to correct errors that have occurred during the configuration of the device from memory.
IE. you gain access to configuration registers and memory, read the error, correct it and then write it back in an attempt to correct the error. Normally this occurs POST configuration.( since you need to load your design to check it.)

The design loads from memory, checks that it is functionally correct then continues, or finds that it is functionally incorrect and attempts a repair.
so to answer the first question no they are not the same.


But all this information to clarify these questions is available on the xilinx site.
for example:

https://www.xilinx.com/support/documentation/application_notes/xapp1088.pdf

it is fairly clear on the process and correction methods.
 
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Hello,

Thanks for your explanation. But I found in the following link that Active Partial Reconfiguration is also called Scrubbing ! I means that scrubbing is noting except Active Partial Reconfiguration. Please have a look on page 15 of this link:
https://www.xilinx.com/support/documentation/application_notes/xapp1088.pdf

Am I right?

Thanks
 

Hi,
It is better to read the whole document in context because one is potentially solution to the other.
If you find an 'error' then you may have to 'reconfigure' the source of that error to remove it.
How else are you going to 'scrub' the error without a 'partial reconfiguration' ( unless you completely re-boot the design ( soft error.. reload the WHOLE FPGA) or totally re-flash the design storage medium(hard error))

So you will see over lapping in the Xilinx descriptions.

1.Consider the case where you have an FPGA design running and the design is 100% correct, but you want to change/improve part of FPGA logic whilst it is running , should this be called 'scrubbing' or 'Partial Reconfiguration'?

2. You have a design that is 100% correct when loaded, but 0.1% got messed up giving a design of 99.9% correct, you have to 'scrub' the 0.1% by doing a 'partial reconfiguration'.

E.G a bicycle has wheels, but having wheels does not make something only a bicycle.


Yes I know it should be clearer and yes it can be very confusing but Xilinx do this quite often because they fail to give CLEAR examples, personally I blame the marketing.
 

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