Parse a VHDL string array

KlausST said:

Hi,

Any editor that can work with "regular expressions" should do.

What OS are you using?

Klaus

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niciki said:

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Code VHDL - [expand]
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component TestRun is
port ( StrAr : in string(1 to 3) :="ABC" );
...
signal Char_Two : character;
 
Char_Two <= StrAr(2); -- ie Char_Two = 'B'

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You don't mean synthesable design, right?

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TrickyDicky said:

The string type in VHDL is defined as:

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Code VHDL - [expand]
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type string is array(positive range <>) of character;

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The Character type is an enumerated type containing all 256 ASCII chars.

So a character cannot be assigned to a std_logic_vector, because they are not the same type.
You will need some form of conversion between the two. The way I would do this using the numeric_std package is:

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Code VHDL - [expand]
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Char_Two <= std_logic_vector(to_unsigned(character'pos(StrAr(1)), 8));

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