Parastic Capcitance of MOSFET

[guomenghan]

Hello everyone:
I want to ask a problem which has confused me for a long time since I first use cadence sprectre to simulate circuit.It is about the intrinsic capacitance of the mos transistor(TSMC.18 process).In the Virtuoso Analog Design Environment,choose DC analysis and save DC operating point.After the DC simulation,choose Result→print→DC operating points，after I click a transistor I could able to find all the DC operating paramators of the transistor.When I check the table,I was confused to find some capacitance totally unfamiliar with me.Especially cdd,cddbi and cjd,cjs.And sometimes I find these paramators play an very important role in my design. I have asked lots of my classmats but still couldn't get the answer.Eager to get the answers from you.
THANK YOU

 

[ic98]

what exactly is your question?!

 

[mkrtich.nazaryan]

guomenghan: As you know SPICE models of MOS transistors can consist a lot of different type passive elements like resistor. capacitors etc as well. So these capacitors which you mention here just using for made up the correct SPICE models for MOS transistors. There is case for example 0.32nm n-channel MOS transistor model can consist 6-7 capacitors, 5-6 resistors and so on. And when you printing out the points by software and didn't mention exactly points the simulator will print out all possible point from all possible elements inside of transistor models.

 

[guomenghan]

I just want to understand the capacitance such as cdd,cddbi and cjd,cjs.I know that the simulator Sprectre of Candence uses BSIM model and I have already downloaded the BSIM3v3 manual reference.But I could not find the parastic capacitance I mentioned above.Thank you

---------- Post added at 19:29 ---------- Previous post was at 19:12 ----------

Thank you very much.From your answer,I learned that such capacitance as cdd,cddbi and so on are just the capacitance to constitute the correct SPICE models.However,I still have two another answers:
1.I have just downloaded the BSIM reference manual and found a lot of capacitances such as CGS0,CGD0,CGB0.But how did the capacitances showed in Candence Sprectre to make up the capacitances demonstrated in SPICE model.Did you have any documents introduce this?
2.I have learned form your answer(I mean the last sentence)that maybe I could able to control the simulator not to print out all the passive elements inside the transistor model.How could I do that?
Very looking forward to your answer and thank you very much.

 

[mkrtich.nazaryan]

dear guomenghan, actually it's very hard to find some documentation. The vendor, I mean the company who provide the BSIM models they have a also a description documentations about model, but usually this type docs is confidential.
Regarding your last question. previously I used only HSipce simulator from Synopsys, I'm not familiar with Candence software, so in this case I can't help you, sorry.
Here is a little part from TSMC 0.18um old RF mos transistor model description:
You can see that they use a lot of Caps, and Resistor and Diodes to made up RF MOS model. and only TSMC can explain why they use for example CGS_M-cap and what is the purpose of this cap.

**************************************
.SUBCKT nmos_rf D G S B lr=18.E-08 nr=64 wr=1.5E-6
.param Lspace=0.54u
.param Ledge=2.6u
.param Ledgeeff=0.97u
.param Lsti=1.84u
.param Wsti=3.37u
.param Rod=2570
.param Rsti=4597
.param Ns='int(nr/2+1)'
.param Nd='int((nr+1)/2)'
.param Lod='nr*(lr+Lspace)+2*Ledge-Lspace'
.param rb='(Rod*Lod/12+Rsti*Lsti/2)*(Rod*wr/12+Rsti*Wsti/2)/(Lod*(Rod*Lod/12+Rsti*Lsti/2)+wr*(Rod*wr/12+Rsti*Wsti/2))'
.param rdb='Rod*lr/(wr*nr*2)'
*********************
RG G GI R='(0.539*wr/nr/lr+0.146/nr/(lr*1e6)+17.86/nr+584.9*lr/nr/wr+3.4'
RS S SI R='(0.0325*(lr*1e6+0.54)*(2*Ns+1/Ns-3) +8.666/Ns + 0.4485)/(wr*1e6)'
RD D DI R='0.005417*(lr*1e6+0.54)*(Nd+2/Nd) + 0.0929*(wr*1e6+2.94)/Nd + 1.625/(1.43+(Nd-1)*(lr*1e6+0.54))'
*********************
CGS_M GI SI C='(1.649*nr*(lr*1e6+0.54)/(0.1*wr*1e6+4)+0.158*wr*1e6+0.737)*1e-15'
CGD_M GI DI C='(0.181*nr*lr*1e6+0.153*nr+0.331)*1e-15'
CDS_M SI DI C='(0.0713+0.0842*nr*wr*1e6/(lr*1e6+0.9)+1.051*nr*(lr*1e6+0.54)/(wr*1e6+9.)*1e-15'
***** Diodes ****************
DSS SB SI ndio_rf_f AREA = '(Ns-2)*wr*Lspace+2*wr*Ledgeeff+(nr-int(nr/2)*2)*wr*(Lspace-Ledgeeff)'
+ PJ='(Ns-2)*Lspace*2+2*(2*Ledgeeff+wr)+(nr-int(nr/2)*2)*(2*(Lspace-Ledgeeff)-wr)'
DDD DB DI ndio_rf_f AREA = 'int(nr/2)*wr*Lspace+(nr-int(nr/2)*2)*wr*Ledgeeff'
+ PJ='int(nr/2)*Lspace*2+(nr-int(nr/2)*2)*(2*Ledgeeff+wr)'
DSG SB SI ndio_rf_g AREA = 1E-15 PJ = 'wr*nr'
DDG DB DI ndio_rf_g AREA = 1E-15 PJ = 'wr*nr'
************************************************** ***************************
RB B BI R='rb'
CB B BI C='159f/rb'
Rdb DB BI R='rdb'
Cdb DB BI C='159f/rdb'
Rsb SB BI R='rdb'
Csb SB BI C='159f/rdb'
******* MOSFET *******
M0 DI GI SI BI nch_rf L = lr W = wr M = nr AD = 0 AS = 0 PD = 0 PS = 0

.MODEL nch_rf.1 NMOS ( LMIN = 1.8e-007 LMAX = '5.001E-07'
+WMIN = '1.5000E-06' WMAX = '8.001E-06'
+LEVEL = 49 TNOM = 25.0 VERSION = 3.24
+TOX = 'toxn_RF'
+TOXM = 4.08E-09
+XJ = 1.6000000E-07
+NCH = 3.9000000E17 LLN = -1 LWN = 1.0000000
+WLN = 1.0000000 WWN = -1 LINT = 1.0000000E-08
+LL = 0.00 LW = 0.00 LWL = 0.00
+WINT = 3.0000000E-09 WL = 0.00 WW = 0.00
+WWL = 0.00 MOBMOD = 1 BINUNIT = 2
+XL = '-0.02E-6+dxln_RF' XW = '0.0+dxwn_RF' DWG = 0.00
+DWB = 0.00 ACM = 12 LDIF = 9.00E-08
+HDIF = 'hdifn_RF' RSH = 'rshn_RF' RD = 0
+RS = 0

*****************************************

 

[guomenghan]

Thank you very much for your answer!

 

[sutapanaki]

Usually Cgg is the total gate capacitance, cdd is the total drain capacitance and so on. And some of those caps can be negative in the model - it is just the way spice/spectre calculates them. Your best bet is to pick a transistor with a given size, put it under some dc conditions, for ex. in saturation, simulate the terminal capacitances in ac analysis and compare to the values that you get from the DC op for the same sized transistor under the same dc conditions. Then you know which cap is which.