parameterized MUX implementation

[rrucha]

Hello

I want to implement a fully parameterized multiplexer. The minimum inputs that it has is 2. Both of them are 16 bit.
What needs to be configurable is the additional number of inputs that can come to the MUX and also, these are all of different widths. I get that the output width of the MUX will be fixed but these input widths need to be variable and also the number of these inputs need to be variable.
Is there any SystemVerilog implementation to realize this logic?

Thanks in advance.

 

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Hello

I want to implement a fully parameterized multiplexer. The minimum inputs that it has is 2. Both of them are 16 bit. What needs to be configurable is the additional number of inputs that can come to the MUX

This is possible using a packed array for the inputs and a parameter to define the number of input ports. Synthesis will work with such an array (at least Vivado synthesis and the newer version of Synplify do).

and also, these are all of different widths. I get that the output width of the MUX will be fixed but these input widths need to be variable and also the number of these inputs need to be variable.
Is there any SystemVerilog implementation to realize this logic?
Thanks in advance.

The requirement for different widths is not possible in any HDL language. HDLs are not some sort of dynamically typed language. Your requirement would need a language that can have an array that is non-

Like I've told you before you use the maximum width input and all inputs are that wide. You will need another parameter (an array) that defines the actual width of each input, which you can then use to slice the bit vectors.

 

[rrucha]

I understand. I figured out the way to do that.
Can I use the same way to create a parameterized DEMUX as well?

 

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Same way as a mux, if you implemented it with max width buses and index the packed array output to select where the input is routed.