Parameterized Analog Cells question

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vparonov

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Hi all!

Is there available tools for design of parameterized analog cells - bias, bandgap, current mirrors etc? I am interested from developer point of view. Any information about such tools will be very helpful (especially open source and free tools).

Thank you in advance for information!
 

Analog Design Automation was a company that used to develop tools for automatic analog design. I don't know if they were bought out by Intel or if they are still offering their tools and services. No free tools though.

If you know the schematic in Cadence/Hspice , then you can parametrize them yourself and run the optimizer.

To parametrize something, you add pPar("whatever") as opposed to entering a design value like 0.25u etc.
- then you generate a symbol.
-when you instantiate it, the CDF box will ask you for a parameter.
-Here you can put a variable like 'k_delta' and let the optimizer figure it out.

The advantage is that you can have the same block with different parameter variable names.

Hope this helps.
 

I used it before. But, now, I encounter problems with the CDL netlister.
Any idea :?:
 

okguy said:
I used it before. But, now, I encounter problems with the CDL netlister.
Any idea :?:
Click to expand...

I encountered this problem, too. I found CDL netlister can deal with "[@w]", but not 'pPar("w")'.
 

you should set CDS_NETLISTING_MODE to analog
 

cyrabbit said:
you should set CDS_NETLISTING_MODE to analog
Click to expand...

Yes, I set CDS_Netlisting_Mode to analog. It is OK for auLVS, but not for CDL. Improper value of environment variable CDS_Netlisting_Mode will cause the netlist procedure fail, not limited to parameter translation.
 

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