Parameter MUX output (SystemVerilog)

Status
Not open for further replies.
B

BartlebyScrivener

Member level 5
Joined
Feb 8, 2012
Messages
90
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Visit site
Activity points
2,081
I am trying to create a module which switches x input data packets to a single output packet according to a one hot input.

If x was a fixed value, I would just create a case statement,

Code: 
    case (onehot)
      4'b0000  : o_data = i_data[0];
      4'b0001  : o_data = i_data[1];
      4'b0010  : o_data = i_data[2];
      4'b0100  : o_data = i_data[3];
      4'b1000  : o_data = i_data[4];
      default : o_data = 'z;
    endcase

But with variable x, how do I define all cases?

Thanks.
 
Last edited:

If you can assert that `onehot` is truly one-hot or 0, then you could use a generate

Code: 
  package mytypes;
    typedef logic [7:0] packet_t;
    endpackage 
       
    module mux #(int X) (
          input logic [X-1:0] onehot,
          input mytypes::packet_t i_data[X],
          output wire mytypes::packet_t o_data
          );
    for(genvar i=0;i<X;i++) begin
       assign o_data = onehot[i] ? i_data[i] : 'z;
    end
    endmodule
 
Thanks, I actually did it like this in the end

Code: 
o_data = 'z;
for(int i = 0; i < X; i++) begin
  if(onehot == (1 << i))
    o_data = i_data[i];
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…