Parallel port pullups

[vsmGuy]

74ls245 breakout board schematic

Hi

What do you think about putting 10K pullups on DATA port and 1K Pullups on STATUS and CONTROL port of DB25 Parallel port connector ?

I intend to use the SPP mode of the Parallel Port(with Output capibility and DATA, and normal direction of CONTROL and STATUS port).

Will this be OK ? Or should I change the resistor values ?

 

[IanP]

If you use an old computer, parallel data line will have something like TTL 374 latch with ≈2.5mA sourcing and ≈20mA sinking capabilities; controll lines inputs will be of TTL 244 type and outputs TTL 05 OC (open collector) with ≈4.7kΩ pullups ..
In the above case I can't see any reason why you should add any pullups at all ..

In contemporary computers there are specialised ICs that can have switchable internal weak pullups, so adding "true resistive" pullups may have some sense, but if you intend to add 10kΩ on all data lines you can do the same on control lines ..

Maybe this can shed some more light on this issue:
http://www.vk2zay.net/article.php/35

If you intend to "play" with the parallel port pins it is always a good idea to protect them ..
The simplest protection can be provided by building a breakout box with 5.1V zener diodes between pin and GND and ≈100-330Ω serial resistor on each pin ..

Regards,
IanP

 

[vsmGuy]

I was looking out more for the relation between rise/fall times of signals wrt pullups.

I have developed my own optoisolated breakout board.

 

[vsmGuy]

Would adding external pullups on a circuit board/motherboard with internal pullups be a bad idea ?

 

[IanP]

The output of the Parallel Port is normally TTL logic levels. The voltage levels are the easy part. The current you can sink and source varies from port to port. Most Parallel Ports implemented in ASIC, can sink and source around 12mA. However these are just some of the figures taken from Data sheets, Sink/Source 6mA, Source 12mA/Sink 20mA, Sink 16mA/Source 4mA, Sink/Source 12mA. As you can see they vary quite a bit. The best bet is to use a buffer, so the least current is drawn from the Parallel Port.

That depends on what your port can source and sink ..
If it can sink and source, say, 20mA, I woldn't bother ..
If it can sink 20mA but source only 2-3mA, you can easily add (as low as) 470Ω on all output pins ..
Adding 10kΩ pullups gives you almost next to nothing ..

Regads,
IanP

 

[vsmGuy]

I am not wanting to make ANY assumptions about the parallel port.. they are as predictable as....

I believe adding 10k pullups on data and 1k on control and status signals would be ok if I were to connect these ports to that of a uC..

Am I wrong ?

 

[IanP]

Take a look at the conceptual diagram of the typical pralallel port .. see picture below ..
From its nature it is not very fast port (please note 2.2nF caps on all data lines) and internal pullups on all control inputs ..
As typical output is similar to the TTL totem pole circuit, it doesn't need any additional pullup ..
So, you are not wrong, however, adding external pullups will not have much effect on the co-operation between the parallel port and a microcontroller ..

Regards,
IanP

 

[tareksamy]

In some cases i had seen that the status port got some problems so it's not internaly pulled up so it's better to use a pull up resistor

 

[vsmGuy]

@tareksamy : Could you please explain a your statement a little more clearly ?

 

[jhbbunch]

if the port pins already have pullups and you add your own pullups you have the pullups in parallel, reducing the effective resistance. Make sure you always buffer the chips with a proper high impedance logic gate because you never know. also, the logic levels are alway iffy nowadays. Is it 5V?, 3.3V? It gets confusing. Design appropriately and you are warned.

 

[vsmGuy]

Hence it will be a better idea to NOT use pullups but use buffer like the 74LS/HC244 on the ports ?

 

[jhbbunch]

If you use 10K pullups you should be alright. The pport is in ASIC chips nowadays and who knows what the specs are. If they were using 4.7K pullups and you go with 4.7k that could be a problem. 10K shouldn't be. Putting them into a proper input buffer should take care of the problem. And don't forget, HC logic gates need pullups because they have CMOS logic levels. HCT has ttl levels. 10K should do the trick.

 

[hbaocr]

you can use IC buffer 74ls245: trigger buffer .
that's very easy

 

[vsmGuy]

Are the values for the pullups ok? Would they be compatible with ANY parallel port?

Or do I SKIP the pullups and DIRECTLY connect buffers?

What would be best to achieve most compatibility of interfacing a paralla lport to a uC like the AT89C52 or PIC/AVR?

 

[ultrabrains]

i did a project on that and i used a 10k pullup resistor

 

[shabab]

No Problem Its Ok

 

[vsmGuy]

@ultrabrains : Can you show us the schematic of the project - atleast the parallel port interface ?