I'm pretty sure at this point you are a software programmer that thinks they can write Verilog Software. Wrong, Verilog is a hardware description language. Your idea of counting (from the software world) is to use a for loop. Won't work for a hardware design i.e. Verilog RTL. If you want to count you need to use a clock and a physical register pluse an adder to increment the output of the counter register and stick the incremented value back into the register. Verilog for loops are used to make multiple copies of what ever is in the for loop. Those copies normally use the index to perform bit-slicing and select an item from an array of some sort.
If you wish to take 15 clock cycles you can left shift the 65-bit data by 15 bits to pad the data. Seems pointless as the shift is really just how the two registers are wired up.
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Whoa, I totally missed that you are zero padding 15
bytes of data to a 65
byte data packet. You should have said something about packets or blocks of data. I was reading your posts as 65
bits, which you never pointed out and corrected anyone on. I realize now my mistake was due to seeing your non-functional code. You should present what you are trying to do in C or pseudo code.
If you are trying to pad with 0's how is your byte data organized? Is your byte data packed
wire [80*8-1:0] data_new? Or is it in an array
wire [7:0] data_new [0:79]? Does your byte data show up as one bit 65-byte word or as 65 individual bytes arriving one after another (streaming)? Depending on the answer you will have to perform different operations to load the 65-bytes into the 80-byte packet.
If the data_new is a large register then I would use a demultiplexer to load each byte (or multiple bytes 65 of them) into the various fields of the 80-byte register. This could be as simple as:
Code:
// direct assignment
assign data_new[80*8-1:0] = {data[65*8-1:0], {15{8'b0}}};
// indexed assignment per byte with array deffinitions
for (i=0;i<80;i=i+1) begin
// i assumes that the most significant bytes of the data_new array are at the lowest index.
assign data_new[i][7:0] = i<16 ? 8'b0 : data[i][7:0];
// If you are little endian then 80-i and 65-i would be used:
// assign data_new[80-i][7:0] = i<65 ? 8'b0 : data[65-i][7:0];
end
All of the above assumes that data and data_new are held in registers so all the bytes can be accessed in parallel. If data and data_new are in a memory or are streaming bytes then you need to have a FSM to monitor the byte stream and load the data_new memory or perform the zero fill padding insertion.