Pad tri state disable case simulation

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dileep4111

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I am doing characterization for bi-directional I/O pad. Help me how to calculate the timing arcs , when the cell is going in to tri-state. Since when the cell in tri-state PAD will be floating, I tried putting some voltage source and did calculations for transition times and Delay values but it is not working. Help with simulation set-up how to calculate the transition time and delay value.
 

This is classic problem as to how to define the tristate. when you are enabling you can set the measurement to reach 90% of the VDD in case of 1 as input and 10% of vdd in case of 0 as input.

For disabling arc, you have to do current reduction from 90% to 10%. when the current going into the load capacitor. These are standard methods supported in any characterization tool like Silicon Smart(Synopsys) or Altos( Cadence). you can over their manual and setup. This is an age old problem so you dont want to spend time inventing a new method ;-)
 

Your simulation is in my opinion best defined in old logic - HC or FACT. This appnote will show you the typical simulation /test circuit and tpzl/tphz definition.

https://www.onsemi.com/pub/Collateral/AND8277-D.PDF

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Your simulation is in my opinion best defined in old logic - HC or FACT. This appnote will show you the typical simulation /test circuit and tpzl/tphz definition.

http://www.onsemi.com/pub/Collateral/AND8277-D.PDF
 
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