Hi friends,
can anybody suggest me or provide me a refrence code ... showing how to design data packet header in VHDL ... the header should contain .. CRC and ACK (address of next coming data packet)
Implementing a stack in hardware has significant limitations, it is much easier to implement just the Ethernet hardware inferace, then implement the stack in code.
However it can be accomplished with limitation:
This link will provide you with the CRC calculation and frame composition. It also discusses many of the limitations when implemented in hardware.