P-Well Layout in TSMC 65nm

[Rams94]

I want to draw a P well like the figure.

I have three layouts that come to mind, but I am confused about which one is right because of the PW layer in TSMC 65nm.

They are the three layouts:

(a) Draw the DNW and draw the NW with an empty center(hole).
(b) After drawing as in (a), draw a PW layer in the center hole.
(c) Draw DNW, draw NW without a hole, and draw PW in the center.

Which one do you think is right?

 

[dustin76]

DNW is like a buried layer and need NW to provide potential. So you should draw DNW without a hole then draw NW like a guard ring and connect to the highest potential. As for PW, I never used TSMC process before, but PW should be operated layer generally means you need not to draw it manually.