P-Type JFET confusion

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Pha5e

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I am confused with the operation of a p-type JFET. I am using a 2N5462 with a 1M Ohm resistor connected to the Gate. The load is between +2.5V and the Drain terminal. The Source is connected to ground.

The JFET conducts with the other end of the 1M Ohm resistor connected to +2.5V and ground? When the resistor is left floating, the load current drops very low but then gradually starts to increase by itself and the JFET begins to partially conduct? :???:
 

Gradual rise is due to charging of internal capacitors of the JFET

Partial conduction in the sense nearly half the actual value when gate is at 2.5 V or else :roll: Do specify
 

With a 330 Ohm resistor as the load, the current through the resistor and JFET is as follows:

Gate resistor grounded: 3.5mA
Gate resistor connected to +2.5V: 2.3mA
Gate resistor floating: Current slowly rises to approximately 1mA

Surely with the gate at +2.5V the JFET should be fully conducting and at ground, it should be off?
 

When it is grounded it does not effectively get turned off A Ptype JFET gets turned off only when a negative voltage is applied

There is a reverse bias but this is not sufficient to pinch off the drain current

So effective drain current exists when the gate is left grounded

Vgs=Vs-Vg = 0-0=0V

So this explains the fact that the FET is yet to go into turn off condition
 


Drain Source interchanging can alter the response curve in the case of an IC I need to work on this to be of more help to you

But for design in paper they can work really cool But I seriously doubt this in practical ckt
 

Surely with the gate at +2.5V the JFET should be fully conducting and at ground, it should be off?
Click to expand...
To turn the P-FET fully off, you have to apply positive Vgs, e.g. +4 or +5 V in your circuit.

Applying a negative Vgs (gate at ground) will in fact further increase the drain current, but also forward bias the gate junction, which is normally unwanted.
 

Just to clarify, JFETs are normally depletion-mode. That means they conduct their maximum current with a zero gate-source bias and you must apply a reverse bias on the gate to turn them off. For a P-JFET this would be a positive gate-source voltage.

An enhancement mode FET, such as a typical MOSFET, will indeed be off with a zero gate-source bias. They require a gate-source bias voltage to conduct (plus polarity for N-MOSFETs and minus polarity for P-MOSFETs).
 

Thanks for all the replies - I found that the JFET fully switches off when a +12V is applied to the Gate via a 1M Ohm resistor. I would have thought +2.5V would have been sufficient however it wasn't enough to switch the JFET off fully?
 

Pha5e said:
Thanks for all the replies - I found that the JFET fully switches off when a +12V is applied to the Gate via a 1M Ohm resistor. I would have thought +2.5V would have been sufficient however it wasn't enough to switch the JFET off fully?
Click to expand...
And why did you think 2.5V would be sufficient:?: If you look at the 2N5462 data sheet (gasp!) you will see that its maximum gate-source cutoff voltage is 9V (for a drain current of 1uA or less).
 

Pha5e said:
Looking at the datasheet I assumed the VGS(off) could be anywhere between 1.8V and 9V?
Click to expand...
That's a correct assumption, which is the range of the manufacturing tolerance. So 2.5V may or may not shut the transistor off, depending upon your particular transistor. That's why you always need to use the worst-case value when designing a circuit.
 

Pha5e said:
I would have thought that you should not design to a manufacturer's maximum specification limit for a component?
Click to expand...
And why did you think that? You use the worst-case limit for reliable design. That may be the maximum value for some specs and the minimum value for others. You have to use some common sense for this. Thus for Vgs(off) you use the maximum value to insure the transistor is off for any device. Conversely when designing a transistor amplifier you would use the minimum value of transistor transconductance to insure it has a minimum value of desired gain.
 

Apart from the problem of expectable Vgs,off range, the setup in the initial post was reported to apply zero Vgs to the P-JFET (source and gate both at 2.5V), so the transistor will be in on-state anyway.
 

FvM said:
Apart from the problem of expectable Vgs,off range, the setup in the initial post was reported to apply zero Vgs to the P-JFET (source and gate both at 2.5V), so the transistor will be in on-state anyway.
Click to expand...
What does "the problem of expectable Vgs, off range" mean. :-?

It's already been established that the transistor is in the ON state with Vgs=0V. Much of the discussion was how to insure that the transistor turned OFF.
 

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