P+resistor as load in diff pair

[John Xu]

Hi,
I have a question on the P+resistor. I am designing an diff pair amplifier which use resistor as load.I selct the p+resistor as load. Can we use it?

My concern is:this resistor is located in nwell. In this nwell, the parasitic pn junction capacitor will affect the bandwidth? This cap is located at the output node, so i am not sure if this concern is necessary. The postlayon can extract this cap?

Alos, in my spice model, I did not found any parasitic cap description on this resistor.

Is any risk in it?

Thanks in advance!

 

[kwkam]

Your concern of parasitic cap is correct. But most of the time it is not the most important in the load of diff pair. You better concern the matching between the resistor pair of the load. Since, the matching of P+ resistor is bad in general. I suggest to use Poly resistor or current mirror as load.

 

[Syukri]

I agreed with above

but don't worry..if u got a matching transistor then choose the pMOS load...

this will ensure the similarities in your layout environment...

If u use poly then there is an area of poly and transistor..harder to match this in my oppinion