im&u
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Hi!
I am a new user of ovm (I used to work with vhdl/verilog based verification methodology)
I am trying to develop a verification environment for a design that communicates with an external adc( spi protocol: cs, sclk etc)
I have some questions:
As I need a model to emulate the behaviour of the adc,
In this cas the test does not control when to generate a transaction on the adc interface, instead it shall wait for the dut to make a request (cs_n goes low).
In which class shall I put the condition "wait (!cs_n)" ? in the test ? transaction? driver ?
Thank you.
I am a new user of ovm (I used to work with vhdl/verilog based verification methodology)
I am trying to develop a verification environment for a design that communicates with an external adc( spi protocol: cs, sclk etc)
I have some questions:
As I need a model to emulate the behaviour of the adc,
should I design it as a systemverilog module ?
- or as an interface with tasks that drive/receive data from/to the dut?
- or I must create an ADC transaction, ADC sequence, ADC sequencer, ADC driver and an ADC interface ?
In this cas the test does not control when to generate a transaction on the adc interface, instead it shall wait for the dut to make a request (cs_n goes low).
In which class shall I put the condition "wait (!cs_n)" ? in the test ? transaction? driver ?
Thank you.