[SOLVED] Overvoltage protection using Schottky barrier diode

[majsta]

I have created Logic Analyzer board using FPGA and ALVC devices(voltage level translators) for investigating CMOS signals and I come across one problem regarding over voltage protection. Logic Analyzer is working perfect but sometimes I "touch" 12V power sources in process of gathering signals. At the end ALVC device is destroyed because he can't solve more then 5V so I need overvoltage protection if I accidentally "touch" some pins higher then 5V.
I need any proposition using SCHOTTKY BARRIER DIODE or something so I can protect my ALVC device from overvoltage inputs.

 

[alexan_e]

Re: Overvoltage protection

I have opened a random ALVC device datasheet https://www.idt.com/document/74alvc162244-datasheet

In the absolute max rating it says IIK Continuous Clamp Current VI < 0 or VI > VCC ±50mA so basically if you add a resistor in each input to limit the clamp current then you will be fine

 

[majsta]

Re: Overvoltage protection

ok thank you I ll give a shot

 

[majsta]

Re: Overvoltage protection

That is not solution because if I add resistor value to drop voltage for 7V (from 12V to 5V) I would end up with problems when I test 5V because that voltage would be also dropped. So I need something like relay who will activate for anything higher then 5V and block it. So is there any solution for this using SCHOTTKY BARRIER DIODE. Real question would be how is this solved on real Logic Analyzers because I have seen that some of them have protection up to 70V when accidentally touched.

 

[alexan_e]

The resistor is not going to drop the voltage, the input resistance of the gates is high so the current is very low and you get no drop.
When the input voltage goes above the Vcc only then the internal clamp diodes conducts and the current increases so you get a voltage drop but that is the out of spec situation we are trying to fix anyway.

 

[abaz]

Its a buffer. Its meant to draw no current when operating within specs. Any current that it does draw will be due to leakage. The data sheet quoted by alexan says +-5uA. When you apply a voltage larger than specified, the internal clamp diode conducts and its at this stage you need to limit the clamping current. You would have to use a limiting resistor if you used extarnal clamping with a schottky as well.

EDIT: oops, Alexan posted the answer before me...

 

[FvM]

That is not solution

Your answer suggests that you didn't yet get the idea of a clamp circuit, as proposed by alex (and typically used in industry standard equipment).

A clamp circuit is different from a voltage divider. It's placed in front of a high impedance input, e.g a CMOS buffer, and only reducing the voltage if one of the clamp diodes gets forward biased. It has to deal with practical restriction like limited bandwidth due to input capcitances and diode leakage currents.

 

[majsta]

I don't know how to thank you all but maybe this will help someone like me. Anyway I m not an engineer and just don't have time to think much on other things because I have very complex project in front of me regarding FPGA devices. So I calculated that 700 ohm resistor should be fine and used 680 ohm one because I didn't have that what I need and everything was fine Now my logic Analyzer working perfect and when I accidentally touch 12V it is detected like high input signal and there is no overheating or anything abnormal so I don't need to worry to destroy anything again. Like I said I m not an engineer and don't have time to investigate this but maybe I ll find some time understand this better and maybe to use it in other projects. It was simple solution for large problem again. Again thank you people and be proud of your knowledge you have no idea how you made me happy when I soldered everything and find out that concept is working. Now there is just curiosity question how But I ll investigate that later like I said

 

[alexan_e]

My suggestion would be to use a higher value, like 10K

The 700 ohm value you have used will draw too much current (in overvoltage situation) and will stress both the measure circuitry and the internal diode