Data-on-layer collisions is one thing (bad) but
there is also a question about the qualification status
of pad-over-circuitry. This may be "no", "sure" or
"maybe". The qualification for particular assembly
processes must ensure that (a) the process itself
is in control and (b) across its control range, the
effects of thermal compression bonding (or wire
bonding, variously) are insignificant to any electrical
performance or long term reliability.
In a tall metal stack this is probably not a problem
(plenty of Z crush room) but may or may not have
been proven by a rigorous qualification. If not, you
will have to get customer and foundry waivers to
make product shippable. In few-levels-metal there
is more chance that the violence of assembly process
will alter device attributes through strain effects.
You might find that qualification avoids the subtle
(analog leakage, noise, matching) and just gets you
to where you can put I/O and ESD circuitry under
its associated pad (convenient as this can be
"plugged into" I/O-specific DRC rules, and less
"exposure" to unacceptable results at qual). Or you
may be allowed "digital" but not "analog" circuitry
as small quantities of digital circuitry don't care
about a bit of elevated leakage, or matching and
noise qualities whatsoever.
The foundry should have an opinion, although I
have encountered blank looks more than once on
this question. And it is not just about the foundry,
but your assembly technology and vendor as a
part of that technology mashup.