Overestimating switching losses in MOSFET

Hello everyone,

Attached is how the voltage switching of a clamped-inductive switching for a MOSFET really looks like. As shown, the voltage falls to a low value before finishing the whole plateau, in other words, only a part of the whole Qgd is needed to switch the voltage from the Bus voltage to a low value.

If one assumes that the voltage falls linearly to its low value (almost ON state voltage) after the whole plateau charge has given, then that results in overestimating the switching losses because we are overestimating the voltage fall/rise time.

I would like to know if anyone knows how to compute that "Q3" charge needed to bring the drain voltage to "Vx" or any rule of thumb of its estimation in order not to overestimate the switching losses, or if it is worth at all... or just go with the overestimation of the switching losses ?

Here is an intent of computing the Q3 charge using the IPB65R420CFD MOSFET because they are giving the switching times at a clamped-inductive test.

First, compute Qgd for the switching test given in datasheet i.e. VDD=400V, ID=5.2A, Vgs=13V, Rg=3.4 ohms.
Qgd_@Vdd=400V = Qgd_@480V - (80*5pF+80*0.5pF/2)=18.6 nC - 0.42 nC=18.18 nC

Second, compute the charge needed to switch the Vds from 90% to 10% which is given in the switching test. Q3_@Vdd=400V =tr_(datasheet) * Igate=7ns * (13-6.4)/3.4 =13.6 nC which is about 3/4 of Qgd_@Vdd=400V.

Any comment on this is much appreciated !

Thanks for sharing. Anyone who has actually designed a SMPS has required to estimate losses.

I am reading from my phone, but once that I can read this on a computer I will post some additional comments.

I do have a quick question:
In your expression where did the “80” came from?

Qgd is the area under the Crss(Vds) curve. I need the area from 0 to 400 V, so it is simply subtracting to the area Qgd@480V has, the rest of the area, which is a rectangle and a triangle on top. The width of the rectangle, which is the same as the base of the triangle, is 480-400=80 V and the height of the rectangle is about 5pF.

I think I have figured it out. "Vx" is a wisely chosen arbitrary value and hence the Q3 charge must be found from the datasheet curve.

First thing I must point out is that Crss varies with Vgs also, so the Capacitance graph in the datasheet which is given at Vgs=0V is to be used when the Vds is higher than V_plateau because the Qgd happens in the Miller Plateau and hence we have a Vgs=V_plateau bias already in the Crss capacitance.
So, in order to have good results, one must use the capacitance graph for Vds range: Vds>Vplateau. But... how low can we go with Vds or in other words, how much above the plateau one should stay with Vds in order to not have a lot of error ?

This is for the LTSpice model of the IPB65R420CFD MOSFET with Cgdmax=1.6nF, Cgdmin=10 pF and a=0.7 at a Vplateau=6.23V (ID=5.2A), in other words, this is from the mathematical model and NOT from datahseet because the datahseet does not allow to see the values of the capacitances at different Vgs levels:
Using the VDMOS Cgd mathematical model which is as follows:
Cgd(Vgd)=(Cgd_max-Cgd_min)/(1+Π/2) *arctg(a*Vgd) +(Cgd_max*(Π/2)+Cgd_min)/(1+Π/2)

Crss_{at Vgs=Vplateau and Vds=40V}= 36 pF
Crss_{at Vgs=0V (because at 0V is where the datasheet shows us the capacitances) and Vds=40V} = 32 pF <--- 11% error

As Vds is reduced, the differences increase, so the error we would have increases as well. A rule of thumb could be that Vds can no go lower than 6 times the plateau level. This rule of thumb can be used when reading the Crss cap in datasheets.

Second, the "Vx" voltage level is arbitrary and has a first limitation which is what I have said above. The above is a limitation to "Vx" because we would need to compute accurately the Q3 charge using the datasheet curve. The point where the Crss cap starts to increase could be a good candidate for the chosen "Vx" level (obviously if it complies with the said above) because not far away the Vds slope in the switching characteristic will start to decrease as Crss increases further.

Since this "Vx" level could not be very close to the ON state Vds voltage, one must adjust the power loss accordingly, resulting always in an overestimation of the switching loss but far more accurate than the usual switching loss which assumes the drain voltage switches during the whole plateau. In other words, one must still use the Qgd-Q3 charge for the rest of the switching and compute the power lost during that time interval. See attached picture for comparison.

Finally, the Q3 charge is simply the area under the Crss curve from the Vbus level down to the "Vx" value one has chosen.
Below is an example in which I chose Vx=10% of Vbus = 40V.
The computation of the Q3 charge using the mathematical model shows that they are in very good agreement with the measured value.

I just skimmed your posts (mainly looked at the images) and I see your point, that approximating Vds as linear (purple curve) will overestimate switching losses vs a more realistic nonlinear curve (green/blue lines).

The shape of Vds is going to depend on the nonlinearity in Coss and Cgd, usually their values will change by a factor of 2-20x between Vds=0 and Vds=Vbdd /2(sometimes more than 100x for Cgd!). For best accuracy the true Vds waveform should be derived using the Coss and Cgd curves from the datasheet. I think that your "Vx" parameter should be very close to the "knee" voltage seen in those capacitance curves.

edit: I took a peak at the ipb65r420 datasheet and it's curves are pretty extreme. You should note that for this FET Qgs<Qgd by a factor of three, which means this device would be quite susceptible to dv/dt induced turn-on...

Thanks for your thorough investigation of the problem and sharing its results. These more accurate results are very valuable for high power converters.

One could use the simpler over-estimated method for lower power converters and err on the safe side of dissipation.