Overcoming the 8:1 width conversion problem

[shaiko]

Hello,

Unfortunately, I just found out that the Xilinx FIFO generator is limited to (no more than) 8:1 ratio when an asymmetric width FIFO is implemented.
I can design a wrapper around a 1:1 ratio FIFO and achieve the same functionality with an FSM and a shift register - but before I do so, I'd like to consult the forum...

Have you come across this limitation ?
How did you solve it ?

 

[vGoodtimes]

The shift register design doesn't sound that bad. The two design concerns will be how the flags are used as well as the mode of the FIFO. This is even more true if you need additional fabric registers for timing purposes anyways.

 

[shaiko]

The shift register design doesn't sound that bad. The two design concerns will be how the flags are used as well as the mode of the FIFO. This is even more true if you need additional fabric registers for timing purposes anyways.

10 hours passed since I found out about the 1:8 limitation - and I'm still angry.
With Xilinx's IP's not being very convenient for manual editing
https://www.edaboard.com/showthread.php?t=373748
It seems like I'll have to design a wrapper around every different implementation of the 1:1 "mother FIFO".
This is really really annoying!

 

[TrickyDicky]

Couldnt you just use 2x 8:1 and a 2:1? Run the 8:1 in parrallel with some front end counter logic to select which fifo to enable.

 

[shaiko]

Couldnt you just use 2x 8:1 and a 2:1? Run the 8:1 in parrallel with some front end counter logic to select which fifo to enable.

The problem is solvable in many ways...I think the shift register approach would yield better performance as it doesn't use an adder.

Confession - I was secretly hoping that you'll prove this 8:1 nonsense wrong like you did with math.real

 

[wtr]

I think you get better answers here than on the Xilinx forum. Even though they are the vendors of your design.

I remember the pain I suffered when trying to use asymmetrical microsemi fifo's with diff clock for read and write.

A cascade/parallel of 1:x fifos could be used, but again you'd need logic to collect the word before feeding it onto the next fifo/stage. I wouldn't imagine this to be portable between vendors. Whereas the shift register and creating word before fifo will be portable.