OV7670+AL422B interfacing with atmega32

have ov7670 with al422b fifo but not able to get the data via usart.actually i am not able to read the data from fifo, i have posted the source code below.
please please please help!!!!
have a look on it and help me!!! where i am making the mistake since i am working on it from two months

MY i2c (sccb) is perfectly working as able to write and read to camera register.

i think i am not able to read fifo properly. (crystal frequency 12MHz)

unsigned char camera_wr(unsigned char add,unsigned char data);
unsigned char camera_rd(unsigned char add,unsigned char *data);
unsigned char camera_init();
void noacknowledge();
void SCCBinit();
unsigned char SCCBwrite(unsigned char camera_data);
void stopSCCB();
void startSCCB();
unsigned char SCCBread();
void usart_send(unsigned char ch);

unsigned char Vsync=0;

#define F_CPU 11059200UL

#define TX_NEWLINE usart_send(0x0d); \
usart_send(0x0a)

#define SDIOC 6
#define SDIOD 7

#define READ_CLK_DDR DDRA
#define READ_CLK_PORT PORTA
#define READ_CLK_PIN PINA
#define READ_CLK_BIT 0

#define WR_EN_DDR DDRA
#define WR_EN_PORT PORTA
#define WR_EN_PIN PINA
#define WR_EN_BIT 1

#define READ_OE_DDR DDRA
#define READ_OE_PORT PORTA
#define READ_OE_PIN PINA
#define READ_OE_BIT 2

#define READ_RST_DDR DDRA
#define READ_RST_PORT PORTA
#define READ_RST_PIN PINA
#define READ_RST_BIT 3

#define SET_HIGH_RD_CLK READ_RST_PORT |= (1<<READ_RST_BIT)
#define SET_LOW_RD_CLK READ_RST_PORT &= ~(1<<READ_RST_BIT)

#define SET_HIGH_WR_EN WR_EN_PORT |= (1<<WR_EN_BIT)
#define SET_LOW_WR_EN WR_EN_PORT &= ~(1<<WR_EN_BIT)

#define SET_HIGH_READ_OE READ_OE_PORT |= (1<<READ_OE_BIT)
#define SET_LOW_READ_OE READ_OE_PORT &= ~(1<<READ_OE_BIT)

#define SET_HIGH_READ_RST READ_RST_PORT |= (1<<READ_RST_BIT);
#define SET_LOW_READ_RST READ_RST_PORT &= ~(1<<READ_RST_BIT);

void usart_init()
{
UCSRB = (1<<TXEN);
UCSRC = (1<<UCSZ1) | (1<<UCSZ0) | (1<<URSEL);
UBRRL = 5 ;//115200 baud rate
}

void usart_send(unsigned char ch)
{
while(!(UCSRA & (1<0)
{
rem=temp%10;
num=rem;
rev=rev*10+rem;
temp=temp/10;
i++;
}

while(i!=0)
{
rem1=num[i-1];
usart_send(0×30+rem1);
i–;
}
}

void init_interrupt()
{

SREG |= 0×80 ;
MCUCR |= 0×03;//INTERRUPT 0 RISING EDGE
GICR = (1<<INT0);//VSYNC rising edge

}

ISR(INT0_vect)
{
if(Vsync==0)
{
SET_HIGH_WR_EN;
Vsync=1;
}
else if(Vsync==1)
{
SET_LOW_WR_EN;
Vsync=2;
}
}

int main(void)
{
unsigned int i=0;
unsigned char j=0,k=0;
unsigned char message[]="CAMERA INITILIAZED";
unsigned char message1[]="YOUR OV7670 SETUP IS READY";

unsigned long a=0;

usart_init();

PORTC=0×00;

READ_RST_DDR |= 1<<READ_RST_BIT;
WR_EN_DDR |= 1<<WR_EN_BIT;
READ_OE_DDR |= 1<<READ_OE_BIT;
READ_CLK_DDR |= 1<<READ_CLK_BIT;

SET_LOW_READ_OE;
SET_LOW_WR_EN;

while(1!=camera_init());

camera_wr(0×15,0×02);
camera_wr(0×11,0×01);
camera_wr(0×12,0×11);
camera_wr(0x0c,0×04);
camera_wr(0x3e,0x1a);
camera_wr(0×70,0x3a);
camera_wr(0×71,0×35);
camera_wr(0×72,0×11);
camera_wr(0×73,0xf9);
camera_wr(0xa2,0×02);

for(k=0;message[k]!='';k++)
usart_send(message[k]);

init_interrupt();
SET_LOW_READ_RST;
SET_LOW_RD_CLK;
SET_HIGH_RD_CLK;
SET_HIGH_READ_RST;

SET_LOW_RD_CLK;
SET_HIGH_RD_CLK;

for(a = 0; a < 38400; a++)
{

SET_LOW_RD_CLK;
SET_HIGH_RD_CLK;

SET_LOW_RD_CLK;
SET_HIGH_RD_CLK;

SET_LOW_RD_CLK;
SET_HIGH_RD_CLK;

SET_LOW_RD_CLK;
SET_HIGH_RD_CLK;

}

while(1)
{
uint32_t count=0;
uint16_t color=0;
if(Vsync==2)
{
SET_LOW_READ_RST;

SET_LOW_RD_CLK;
SET_HIGH_RD_CLK;

SET_HIGH_READ_RST;

SET_LOW_RD_CLK;
SET_HIGH_RD_CLK;

for(count=0;count<76800;count++)
{
SET_LOW_RD_CLK;

SET_HIGH_RD_CLK;
color= (PINC <<8) & 0xff00;

SET_LOW_RD_CLK;
SET_HIGH_RD_CLK;
color |= (PINC) & 0x00ff;

usart_send_data(color);

}
Vsync=0;



}
}