Outputting 4 Phase Shifted Clocks

If you have already pinned down the ODDR2 locations, then finding a DCM location close to is should be reasonably doable in planahead. You want to have the ODDR2's and the DCM to be in the same clock region. Those should have differently colored boxes in planahead. If you have all your DDR stuff in the X1Y1 region then you should put your DCM + buffer in that region as well.

Dear Mrflibble,

A few years ago (17-03-11) you answered a post regarding Clock output from FPGA. The person who posted it was running into several mapping errors, at one point you responded stating that they should read the documentation on IODELAY2 for the spartan-6 to help better understand how to properly map components to the FPGA. By chance do you remember what the document you were referring to? Also will this help with mapping errors that I'm facing on my spartan-3e board?

Here is the original thread:
https://www.edaboard.com/threads/206190/

loki3118 said:

By chance do you remember what the document you were referring to?

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From the old thread:

mrflibble said:

On that subject, UG381 chapter 2 has some useful info.

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As for your other question if it will help ... Not sure, but reading the docs for IO resources tends to take away some of the confusion.

I apologize that this is taking so long for me to figure it out. Your help is greatly appreciated!
I thought that I had the correct locations for the ODDR2 however, I quickly realized that the locations were not correct.

I've come to the understanding that it requires a lot of knowledge to properly place each component in PlanAhead. I believe that my DCM global clocks correct due to there being only 4 places to put them in one region. I placed another clock in a local routing location due to not having enough global clocks, I tried to place it as close to my DCM as possible. However, I'm running into trouble placing my ODDR2 instances and my clock outputs. I feel this is due to lacking the understanding of what each instance requires on the FPGA.

Can Outputs go on any I/O pin? Also what is the proper pin type for ODDR2? Finally, in a previous post you mentioned that my "DCM + buffer" need to be in the same region as everything else, what do you mean by buffer in this case?

Buffer being BUFG I think in that case, but the recommendation within that context (how do I get everything optimal blah blah blah) is to put the whole shebang in the same clock region. Which should be no big deal if you have a small design.

But if you use coregen it will automatically create them buffers for you and plonk it in the right place ... most of the time.

Can outputs go on any I/O etc ... the pin capabilities for your chosen fpga should be in the datasheet, but I think you can also pointey clickey that together in planahead (floorplanner). As for can any output go on any IO. If I understand your question correctly, then yes. But some combos are not possible. As in suppose you want a differential output, then you are restricted to certain pairs of pins. That sort of thing.

Inputs are somewhat more restrictive, mainly with respect to clock inputs.

I would suggest reading some more of that pdf I linked to. It might seem a bit much, but it's doable. Page 12 is a good location to go and read a few pages until you go gaaaaaaaaaah. Maybe 12-24 or so, that should give you a good idea.

Thank you for the suggestions! Ill be sure to read 12-24 till my eyes fall out! After I put my eyes back into their respective socket Ill keep reading then give it another try! Your words of wisdom has been invaluable!

The recommend reading is helping out quite a bit! I do have a quick question, I hope. Do you have to place all of the signals in PlanAhead? Or is there a way to map only specific ones and let ISE place the remaining signals?

I've placed my DCM, global clocks, and output signals but nothing else. I would like everything else placed in an optimal place according to these constraints.

loki3118 said:

I've placed my DCM, global clocks, and output signals but nothing else. I would like everything else placed in an optimal place according to these constraints.

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For quite a lot of designs that is sufficient. You don't really need (or want) to make placement constraints for everything. If only because writing & maintaining those constraints is more work.

The bare minimum sensible amount of constraints is your pin assignments, assuming you want your signals to go somewhere in the outside world. However, when the design gets larger / faster you may find that you need to write more constraints. Placement constraints of logic blocks isn't much of an issue when things are slow enough, but when your design doesn't meet timing you often have to place this here and that there. Placement makes a BIG difference in routing results, and routing in turn will determine your timings.