Outputting 4 Phase Shifted Clocks

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loki3118

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Hello,

I'm having some trouble figuring out a way to output 4 phase shifted clocks from a DCM on a Spartan-3E board. After reading several different data sheets and different peoples struggle I was under the impression that in order to output a clock to a specific pin on a FPGA you need to use ODDR2. However, I'm not sure that this would be possible with my desired configuration. Is there a better way to output the 4 phase shifted clocks? Or do I have to use ODDR2 for each of the phases out of the DCM?

Any help would be greatly appreciated

Using:
VHDL
ISE 14.5
Xilinx Spartan-3E board
 

ODDR2 is the easy way to do it yes. And you'd only need 2 clock nets for that. One clock at 0 degrees (clk_0) and one at 90 degrees (clk_90). Then you feed two ODDR2's with clk_0. One with 2'b01, and one with 2'b10 inputs. And two ODDR's clocked by clk_90, again one with 2'b01, and the other ODDR with 2'b10 inputs.
 

Thank you for the quick response!

I apologize in advance if i say something stupid, I'm still fairly new to programming an FPGA.

If I understand what your saying it seems like you recommend implementing ODDR2 4 times? Could you explain your notation about 2'b01 and 2'b1?
Also do you know of a good example/tutorial on how to properly declare and implement ODDR2?
 

Take a look at the documentation for the ODDR2 primitives and you'll get what I mean by it. For each pair of ODDR2's one has inputs Q0 = 0 and Q1 = 1, and the other you has inputs Q0 = 1 and Q1 = 0. You have two of those pairs, one pair is clocked by clk_0 and the other by clk_90.

How to implement it, see for example: https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_5/spartan3e_hdl.pdf

Page 142 describes the ODDR2 primitive and shows some VHDL and verilog code templates.
 

Thank you for the clarification! I appreciate your fast response!

I'll give it a shot after reading the ODDR2 primitive documentation. If I run into any troubles I'll post my code!
 

Hello Mr. Flibble,

I've spent a good deal of time this weekend trying to figure out how to implement the ODDR2 clock nets. I have several questions that arose from your previous comments.
So to the best of my knowledge you described a system that uses 4 ODDR2 to forward clk_0, clk_90, clk_180, and clk_270. After reading the documentation on the Xilinx Clocking Wizard to one instance of the ODDR2. It appears that to avoid introducing any duty-cycle distortion I should implement a 180 phase shifted signal. You mentioned to employ two clk_0 signals and two clk_90 signals. These signals will be feed into C0, however what will C1 be?

Clock Net 1
c0(clk_0) with c1(clk_0)
c0(clk_0) with c1(clk_180)

Clock Net 2
c0(clk_90) with c1(clk_90)
c0(clk_90) with c1(clk_270)
Will this allow for outputting all of the clocks to pins?

In addition What DDR flip-flop selection would you recommend. I have reviewed all of the different selections however, I do not have enough experience to make the proper decision let alone know if it really matters.

Thanks for any help!
 


Yup, you are exactly right that the suggested approach has some impact on duty cycle requirements. Because if for example clk_0 doesn't have an exact 50% duty cycle, then the 180 degree output of the ODDR2 will not be exactly 180 degrees. I did think about bringing that one up in the previous post, but naaah lets keep it simple. But I am glad you found out yourself by reading the docs. Anyways, one way to mitigate any duty cycle imperfections on your source clock is to double the clock and then divide by two with the DCM.

That does take up some DCM resources, but does take up only 2 clock nets instead of 4. Or if you feel paranoid about this then you can use 4 seperate clocks each 90 degrees apart. It depends a bit on your exact requirements and how many clock nets are taken up by your other logic.

In addition What DDR flip-flop selection would you recommend. I have reviewed all of the different selections however, I do not have enough experience to make the proper decision let alone know if it really matters.
Click to expand...

Not sure what you mean here? What selection? Do you mean alignment?
 

Thank you Mr. Flibble for your help!

At this early stage in my design, I don't mind programming a resource heavy code. Don't worry it will not become a habit! This is setting up the ground work for a design that requires accurate duty cycle recreation from the output of the ODDR2.

If I wanted to use 4 clock nets, each one with a clock that is 90deg apart, how would you recommend setting up all the necessary CLK180s for each ODDR2?

To clear up any confusion that by last comment may have generated this is a section from Xilinx ISE Help page on Clocking Wizard - Clock Forwarding / Board Deskew

DDR flip-flop selection
The block diagram shows only those connections between the DCM and the specified Double Data Rate (DDR) register. Other DDR register pins, such as CE and R, are connected as ports and are named CE_IN and R_IN respectively.
For more information about each of the following DDR registers, see the Libraries Guides.
OFDDRCPE
A DDR output D register with clock enable (CE), asynchronous preset (PRE), clear (CLR), and one output buffer.
OFDDRRSE
A DDR output D register with synchronous reset (CE), set (S), clock enable (CE), and one output buffer.
OFDDRTCPE
A DDR output D register with clock enable (CE) and asynchronous preset, clear, and a 3-state output buffer.
OFDDRTRSE
A DDR output D register with clock enable, synchronous reset, set, and a 3-state output buffer.
None
DDR register and BUFG are not used in this configuration. CLK0, CLK2X and CLKFX of DCM connect directly to OBUF for external feedback. When the application permits, consider this configuration to save BUFG resources.
 
Last edited:

Without knowing any of your other requirements I think you'll probably want to use this one:

OFDDRRSE
A DDR output D register with synchronous reset (CE), set (S), clock enable (CE), and one output buffer.
Click to expand...

As for creating clk_0, ckl_90, clk_180 and clk_270 ... isn't that reasonably straightforward with the clocking wizard? What version of ISE are you using?

- - - Updated - - -

Forgot to ask: what is your source clock frequency, and what frequency should those clk_0, clk_90 etc be?
 

Thank you for the reply!

In regards to my clock frequency, I was planning on using the DCM to get 4 channels at 32MHz each.

Im using ISE 14.5. The clock wizard is straight forward. My confusion comes from properly assigning the port map to properly instantiate the ODDR2. I included a copy of my code.

Basically I would like to output the 4 phase shifted clocks that run my 4 counters. I went though and tried my best to fill out the port map but there were a few I was unsure about. I underlined the components in port map that i was unsure about.

In addition do I specify the output pins using PlanAhead once the ODDR2 is set up for each channel?

Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
entity Counter4 is
    Port ( clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           DIRECTION0 : in  STD_LOGIC;
           DIRECTION90 : in  STD_LOGIC;
           DIRECTION180 : in  STD_LOGIC;
           DIRECTION270 : in  STD_LOGIC;
           COUNT_OUT0 : out  STD_LOGIC_VECTOR (3 downto 0);
           COUNT_OUT90 : out  STD_LOGIC_VECTOR (3 downto 0);
           COUNT_OUT180 : out  STD_LOGIC_VECTOR (3 downto 0);
           COUNT_OUT270 : out  STD_LOGIC_VECTOR (3 downto 0));
end Counter4;
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
architecture Behavioral of Counter4 is
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
	COMPONENT DCM4
	PORT(
		CLKIN_IN : IN std_logic;
		RST_IN : IN std_logic;          
		CLKIN_IBUFG_OUT : OUT std_logic;
		CLK0_OUT : OUT std_logic;
		CLK2X_OUT : OUT std_logic;
		CLK90_OUT : OUT std_logic;
		CLK180_OUT : OUT std_logic;
		CLK270_OUT : OUT std_logic;
		LOCKED_OUT : OUT std_logic
		);
	END COMPONENT;
----------------------------------------------------------------------------------	
	COMPONENT ODDR2_0
	PORT(
		CE_IN : IN std_logic;
		CLKIN_IN : IN std_logic;
		RST_IN : IN std_logic;
		R_IN : IN std_logic;
		S_IN : IN std_logic;          
		CLKIN_IBUFG_OUT : OUT std_logic;
		CLK0_OUT : OUT std_logic;
		CLK2X_OUT : OUT std_logic;
		CLK180_OUT : OUT std_logic;
		DDR_CLK0_OUT : OUT std_logic;
		LOCKED_OUT : OUT std_logic
		);
	END COMPONENT;
----------------------------------------------------------------------------------
	COMPONENT ODDR2_90
	PORT(
		CE_IN : IN std_logic;
		CLKIN_IN : IN std_logic;
		RST_IN : IN std_logic;
		R_IN : IN std_logic;
		S_IN : IN std_logic;          
		CLKIN_IBUFG_OUT : OUT std_logic;
		CLK0_OUT : OUT std_logic;
		CLK2X_OUT : OUT std_logic;
		CLK180_OUT : OUT std_logic;
		DDR_CLK0_OUT : OUT std_logic;
		LOCKED_OUT : OUT std_logic
		);
	END COMPONENT;
----------------------------------------------------------------------------------
	COMPONENT ODDR2_180
	PORT(
		CE_IN : IN std_logic;
		CLKIN_IN : IN std_logic;
		RST_IN : IN std_logic;
		R_IN : IN std_logic;
		S_IN : IN std_logic;          
		CLKIN_IBUFG_OUT : OUT std_logic;
		CLK0_OUT : OUT std_logic;
		CLK2X_OUT : OUT std_logic;
		CLK180_OUT : OUT std_logic;
		DDR_CLK0_OUT : OUT std_logic;
		LOCKED_OUT : OUT std_logic
		);
	END COMPONENT;
----------------------------------------------------------------------------------
	COMPONENT ODDR2_270
	PORT(
		CE_IN : IN std_logic;
		CLKIN_IN : IN std_logic;
		RST_IN : IN std_logic;
		R_IN : IN std_logic;
		S_IN : IN std_logic;          
		CLKIN_IBUFG_OUT : OUT std_logic;
		CLK0_OUT : OUT std_logic;
		CLK2X_OUT : OUT std_logic;
		CLK180_OUT : OUT std_logic;
		DDR_CLK0_OUT : OUT std_logic;
		LOCKED_OUT : OUT std_logic
		);
	END COMPONENT;
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
signal count_int0 : std_logic_vector(3 downto 0) := "0001";
signal count_int90 : std_logic_vector(3 downto 0) := "0001";
signal count_int180 : std_logic_vector(3 downto 0) := "0000";
signal count_int270 : std_logic_vector(3 downto 0) := "0000";
signal locked : std_logic;
signal clk0 : std_logic; -- stores clock from DCM
signal clk90 : std_logic; -- stores clock from DCM
signal clk180 : std_logic; -- stores clock from DCM
signal clk270 : std_logic; -- stores clock from DCM
signal ODDR2_clk0 : std_logic; -- used to output the clock signal?
signal ODDR2_clk90 : std_logic; -- used to output the clock signal?
signal ODDR2_clk180 : std_logic; -- used to output the clock signal?
signal ODDR2_clk270 : std_logic; -- used to output the clock signal?
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
	Inst_DCM4: DCM4 PORT MAP(
		CLKIN_IN => clk,
		RST_IN => reset,
		CLKIN_IBUFG_OUT => open,
		CLK0_OUT => clk0,
		CLK2X_OUT => open,
		CLK90_OUT => clk90,
		CLK180_OUT => clk180,
		CLK270_OUT => clk270,
		LOCKED_OUT => locked
	);
----------------------------------------------------------------------------------
	Inst_ODDR2_0: ODDR2_0 PORT MAP(
		[B][U]CE_IN => ,[/U][/B]
		CLKIN_IN => clk0,
		RST_IN => reset,
		R_IN => 0, -- unsure if this is correct
		S_IN => 0, -- unsure if this is correct
		CLKIN_IBUFG_OUT => open,
		CLK0_OUT => ODDR2_clk0, -- stores the clock to be forward?
		[B][U]CLK2X_OUT => ,[/U][/B]
		[B][U]CLK180_OUT => ,[/U][/B]
		[B][U]DDR_CLK0_OUT => ,[/U][/B]
		LOCKED_OUT => locked
	);
----------------------------------------------------------------------------------
	Inst_ODDR2_90: ODDR2_90 PORT MAP(
		[B][U]CE_IN => ,[/U][/B]
		CLKIN_IN => clk90,
		RST_IN => reset,
		R_IN => 0, -- unsure if this is correct
		S_IN => 0, -- unsure if this is correct
		CLKIN_IBUFG_OUT => open,
		CLK0_OUT => ODDR2_clk90, -- stores the clock to be forward?
		[B][U]CLK2X_OUT => ,[/U][/B]
		[B][U]CLK180_OUT => ,[/U][/B]
		[B][U]DDR_CLK0_OUT => ,[/U][/B]
		LOCKED_OUT => locked
	);
----------------------------------------------------------------------------------
	Inst_ODDR2_180: ODDR2_180 PORT MAP(
		[B][U]CE_IN => ,[/U][/B]
		CLKIN_IN => clk180,
		RST_IN => reset,
		R_IN => 0, -- unsure if this is correct
		S_IN => 0, -- unsure if this is correct
		CLKIN_IBUFG_OUT => open,
		CLK0_OUT => ODDR2_clk180, -- stores the clock to be forward?
		[B][U]CLK2X_OUT => ,[/U][/B]
		[B][U]CLK180_OUT => ,[/U][/B]
		[B][U]DDR_CLK0_OUT => ,[/U][/B]
		LOCKED_OUT => locked
	);
----------------------------------------------------------------------------------
	Inst_ODDR2_270: ODDR2_270 PORT MAP(
		[B][U]CE_IN => ,[/U][/B]
		CLKIN_IN => clk270,
		RST_IN => reset,
		R_IN => 0, -- unsure if this is correct
		S_IN => 0, -- unsure if this is correct
		CLKIN_IBUFG_OUT => open,
		CLK0_OUT => ODDR2_clk270, -- stores the clock to be forward?
		[B][U]CLK2X_OUT => ,[/U][/B]
		[B][U]CLK180_OUT => ,[/U][/B]
		[B][U]DDR_CLK0_OUT => ,[/U][/B]
		LOCKED_OUT => locked
	);
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
process (clk0) 
begin
	if clk0='1' and clk0'event then
		if DIRECTION0='1' then
			count_int0 <= count_int0 - 1;
		else
			count_int0 <= count_int0 + 1;
		end if;
	end if;
end process;
COUNT_OUT0 <= count_int0;
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
process (clk90) 
begin
	if clk90='1' and clk90'event then
		if DIRECTION90='1' then
			count_int90 <= count_int90 - 1;
		else
			count_int90 <= count_int90 + 1;
		end if;
	end if;
end process;
COUNT_OUT90 <= count_int90;
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
process (clk180) 
begin
	if clk180='1' and clk180'event then
		if DIRECTION180='1' then
			count_int180 <= count_int180 - 1;
		else
			count_int180 <= count_int180 + 1;
		end if;
	end if;
end process;
COUNT_OUT180 <= count_int180;
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
process (clk270) 
begin
	if clk270='1' and clk270'event then
		if DIRECTION270='1' then
			count_int270 <= count_int270 - 1;
		else
			count_int270 <= count_int270 + 1;
		end if;
	end if;
end process;
COUNT_OUT270 <= count_int270;
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
end Behavioral;
 
Last edited:

Regarding portmaps for ODDR's, you can set CE (clock enable) to 1.

And, ehr, wut? You got a bit creative there I think. The portmap for those ODDR2's look like DCMs, what with the CLK2X_OUT and all that.

Check the spartan-3e doc I linked earlier, and check ODDR2, the VHDL instantiation template. That is what your DDR2 goodies should look like. Right now you seem to mixing things up a bit.

I'll cut & paste the part of the docs I mean:

 

Thank you for your continuing help!

How I got to those port maps was through the HDL Instantiation Template that ISE Clock Wizard Generated. Below is a direct copy of what the Clock Wizard gave me. I do see your point that the documentation for ODDR2 Instantiation is fairly different than the ODDR2 that the Clock Wizard Generates. Is there one that is more appropriate to use within the code? Besides "being creative" with the instantiation template is the method above a viable solution?

Code: 
-- VHDL Instantiation Created from source file ODDR2_0.vhd -- 17:23:28 07/11/2013
--
-- Notes: 
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit

	COMPONENT ODDR2_0
	PORT(
		CE_IN : IN std_logic;
		CLKIN_IN : IN std_logic;
		RST_IN : IN std_logic;
		R_IN : IN std_logic;
		S_IN : IN std_logic;          
		CLKIN_IBUFG_OUT : OUT std_logic;
		CLK0_OUT : OUT std_logic;
		CLK2X_OUT : OUT std_logic;
		CLK180_OUT : OUT std_logic;
		DDR_CLK0_OUT : OUT std_logic;
		LOCKED_OUT : OUT std_logic
		);
	END COMPONENT;

	Inst_ODDR2_0: ODDR2_0 PORT MAP(
		CE_IN => ,
		CLKIN_IN => ,
		RST_IN => ,
		R_IN => ,
		S_IN => ,
		CLKIN_IBUFG_OUT => ,
		CLK0_OUT => ,
		CLK2X_OUT => ,
		CLK180_OUT => ,
		DDR_CLK0_OUT => ,
		LOCKED_OUT => 
	);
 

I think that the confusion comes from mixing the name ODDR2 in the clocking wizard. ODDR2 per se has nothing to do with clocking resources. It just so happens that using ODDR2's is a handy way to output clock signals.

Did you happen to give a funky ODDR2 name to a DCM module generated from core generator? The above map looks like a DCM, and not at all like a DDR2. If so, I propose that you rename your DCM modules to something that reflects it's DCM-iness, and lack of ODDR2-iness. Otherwise it's just confusing.

Also, check out the DCM_SP primitive in that PDF I linked to (page 28). You'll see it is suspiciously much the same as your "ODDR2", and not at all the same as a "proper ddr2". ;-)
 

Thank you for the quick reply!

I believe your right that the confusion comes from using the clock wizard. My next course of action is to simply disregard the clock wizard to generate the ODDR2 and instead use the library that you keep specifying. I'm going to try my best to use the proper ODDR2 Instantiation that you recommended. Ill post my results at a later time.

I apologize for any confusion that I might of caused and I really appreciate the help!
 

Nothing wrong with using the clocking wizard to generate DCM modules. Just don't expect them to magically have anything to do with DDR2 registers, and name those DCM modules appropriately and you'll be fiiiiiine. But, the approach as you suggest to just use the DCM_SP instantiations cannot hurt. At least that way you will have to read that part of the docs, so you'll be better informed than just pointey-clickey in the wizard.

At any rate, you should be able to do what you want by just using the DCM_SP and ODDR2 primitives.
 

Thanks you!

My problem came from using the clock wizard to generate the ODDR2. I successfully generated the DCM previously before attempting to use ODDR2. My confusion came from misunderstanding what the capabilities of the clock wizard. I was under the impression that it was possible to use the clock wizard to forward the clocks which was why I was so intent on using the primitives I posted. This misunderstanding also explains the confusion about why my ODDR2 looked so similar to my DCM, they were in fact both generated in a way that is suitable for DCM.

I would like to reach a level of deep understanding in both the ISE environment and programming in VHDL for FPGAs. However, I've learned that there is a steep learning curve, coupled with little explanation in the documentation. Without your help, I would still be under the impression that those primitives would work for ODDR2 despite their striking similarity to DCM.
 

Could you explain what the purpose of the following?
CE => CE, -- 1-bit clock enable input
D0 => D0, -- 1-bit data input (associated with C0)
D1 => D1, -- 1-bit data input (associated with C1)
R => R, -- 1-bit reset input
S => S -- 1-bit set input

Im trying to porperly fill out the Instantiation of ODDR2, however I am not sure what belongs in these places. Is there a place that I could read more about the significant of these declarations?
Below is the latest update to my code, hopefully it makes more sense.

Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
entity Counter4 is
    Port ( clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           DIRECTION0 : in  STD_LOGIC;
           DIRECTION90 : in  STD_LOGIC;
           DIRECTION180 : in  STD_LOGIC;
           DIRECTION270 : in  STD_LOGIC;
           COUNT_OUT0 : out  STD_LOGIC_VECTOR (3 downto 0);
           COUNT_OUT90 : out  STD_LOGIC_VECTOR (3 downto 0);
           COUNT_OUT180 : out  STD_LOGIC_VECTOR (3 downto 0);
           COUNT_OUT270 : out  STD_LOGIC_VECTOR (3 downto 0));
end Counter4;
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
architecture Behavioral of Counter4 is
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
	COMPONENT DCM
	PORT(
		CLKIN_IN : IN std_logic;
		RST_IN : IN std_logic;          
		CLKIN_IBUFG_OUT : OUT std_logic;
		CLK0_OUT : OUT std_logic;
		CLK2X_OUT : OUT std_logic;
		CLK90_OUT : OUT std_logic;
		CLK180_OUT : OUT std_logic;
		CLK270_OUT : OUT std_logic;
		LOCKED_OUT : OUT std_logic
		);
	END COMPONENT;
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
signal count_int0 : std_logic_vector(3 downto 0) := "0001";
signal count_int90 : std_logic_vector(3 downto 0) := "0001";
signal count_int180 : std_logic_vector(3 downto 0) := "0000";
signal count_int270 : std_logic_vector(3 downto 0) := "0000";
signal locked : std_logic;
signal clk0 : std_logic; 
signal clk90 : std_logic; 
signal clk180 : std_logic; 
signal clk270 : std_logic; 
signal clk0_out : std_logic; 

----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
	Inst_DCM: DCM PORT MAP(
		CLKIN_IN => clk,
		RST_IN => reset,
		CLKIN_IBUFG_OUT => open,
		CLK0_OUT => clk0,
		CLK2X_OUT => open,
		CLK90_OUT => clk90,
		CLK180_OUT => clk180,
		CLK270_OUT => clk270,
		LOCKED_OUT => locked
	);
----------------------------------------------------------------------------------
ODDR2_inst : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
port map (
Q => clk0_out, -- 1-bit output data
C0 => clk0, -- 1-bit clock input
C1 => clk180, -- 1-bit clock input
CE => 1, -- 1-bit clock enable input
D0 => 1, -- 1-bit data input (associated with C0)
D1 => 1, -- 1-bit data input (associated with C1)
R => reset, -- 1-bit reset input
S => 1 -- 1-bit set input
);
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
process (clk0) 
begin
	if clk0='1' and clk0'event then
		if DIRECTION0='1' then
			count_int0 <= count_int0 - 1;
		else
			count_int0 <= count_int0 + 1;
		end if;
	end if;
end process;
COUNT_OUT0 <= count_int0;
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
process (clk90) 
begin
	if clk90='1' and clk90'event then
		if DIRECTION90='1' then
			count_int90 <= count_int90 - 1;
		else
			count_int90 <= count_int90 + 1;
		end if;
	end if;
end process;
COUNT_OUT90 <= count_int90;
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
process (clk180) 
begin
	if clk180='1' and clk180'event then
		if DIRECTION180='1' then
			count_int180 <= count_int180 - 1;
		else
			count_int180 <= count_int180 + 1;
		end if;
	end if;
end process;
COUNT_OUT180 <= count_int180;
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
process (clk270) 
begin
	if clk270='1' and clk270'event then
		if DIRECTION270='1' then
			count_int270 <= count_int270 - 1;
		else
			count_int270 <= count_int270 + 1;
		end if;
	end if;
end process;
COUNT_OUT270 <= count_int270;
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
end Behavioral;
 

set CE=1, set R=0, and D0 and D1 as discussed waaaaaaaay back before you got confuzzled by decoy DCMs.

You can read about the DDRs in the manual for the spartan-3e fpga. The pdf that describes slices and their content.

Real quick look at your code... you have D0 = 1 and D1=1 for the same DDR register, which is not the idea. Maybe re-read the start of the thread to get back to the original idea.
 

Random addition:

If you are going with 4 clock nets, each 90 degrees apart, then: CE=1, R=0 and D0=0, D1=1 for each of the four DDRs you will need. That way you will have 4 clock outputs, 90 degrees apart. Used this way you can think of those DDR's as simple output buffers for your clock nets.
 

I believe that I'm at the point where I could use the floorplan Area/IO/Logic (PlanAhead) to route the ODDR2 to specific pins, however I came across this error (included blow). After doing a little research, apparently one possible solution is to manually place the DCM to specific pins. However, I wasn't sure how to properly specify the DCM location within the floorplan. If you have any recommendations on documentation to read to learn more about pin placement on the FPGA it would be greatly appreciated.

Place:962 - A DCM / BUFGCTRL clock component pair have been found that are not placed at an optimal DCM / BUFGCTRL site pair. The DCM component <Inst_DCM4/DCM_SP_INST> is locked to site <DCM_X0Y1> and the corresponding BUFGCTRL component <Inst_DCM4/CLK2X_BUFG_INST> is locked to site <BUFGMUX_X1Y1>. This will not allow the usage of the fast path between the DCM and the Clock buffer. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING and allow your design to continue. However, the use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. A list of all the COMP.PINs used in this clock placement rule is listed below. These examples can be used directly in the .ucf file to override this clock rule.
< PIN "Inst_DCM4/DCM_SP_INST.CLK2X" CLOCK_DEDICATED_ROUTE = FALSE; >
 

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