Output voltage of Boost PFC circuit is higher than calculated?

[treez]

Hello,
A contractor has designed a Boost PFC circuit for us. He has used the FL6961 PFC controller. He insists that he has set the PFC output voltage to 418V. However, the output divider has a top resistance of 2.04 Megohms, and a bottom resistor of 13K…….in my calculation this would give a PFC output voltage of 395V? (since the internal reference voltage is 2.5V)

So which of us is correct?

Certainly if there was eleven microamps of leakage current going into the “INV” pin of the FL6961 then that would push the output voltage up to 418V, but the datasheet doesn’t mention any leakage at all in the “INV” pin of the FL6961.


FL6961 datasheet:
https://www.fairchildsemi.com/datasheets/FL/FL6961.pdf

 

[E-design]

What are the tolerances on the resistors? This will play a significant role and even more with temperature changes. You may have to do a worst case or a Monte Carlo analysis to see this.

 

[treez]

Thanks, They are 1% resistors, so wouldnt be an effect here....not to give an extra 23V

 

[E-design]

Is it still just a paper design or working product that you can verify your concerns by measurements?

- - - Updated - - -

“One good test is worth a thousand expert opinions.”

― Wernher von Braun

 

[treez]

Thanks, but i dont have access to the PSU due to only a few of us being allowed access to it. The few prototypes we have are strictly for our emc dept only. They are too busy with other stuff at the mo.

 

[E-design]

If you look at the manufacturing tolerance of the internal reference and variation vs temperature in the data sheet together with the tolerances from the 1% resistors, it appears highly unlikely to have such a large error in the output voltage.

 

[Dan Mills]

What does the bus cap voltage actually measure?

You have noticed the approximately 100mV change in the reference with temperature on the graphs, maybe the thing was designed for some particular operating temperature?

Have you tried asking the guy who did the design to explain it to you, 'tis good practice to have a design review with the consultant prior to handover.

Regards, Dan.

 

[treez]

The big unknown here, is what is the leakage current into the INV pin, -the datasheet doesnt say, and fairchilsemi dont give product support to uk...or at least ive never seen such

 

[FvM]

It's OK to complain about incomplete specification, apparently you have reasons to use the part despite of the bad support.

Did you ever consider to measure the typical INV pin input current?

 

[D.A.(Tony)Stewart]

With 13k and +/-20uA typical bias current input offset is typically 260mV or +\-1%

Tolerance on Vref=2.50 is 25mV or 1% but the error amp is reported in text to be connected Vref with 2% accurate, in Fairchild's spec.

With each R at 1% with have a total detection error of ~5% about 394.8.

This assumes the primary windings are matched, which we cannot guess.

The designer indicated a result 5.8% higher for some reason. Is this worstcase?, I suppose.

 

[treez]

thanks, -if the bias current is up to 20uA into the INV pin, then that explains it....the flow of the bias current through the 2.04 Megs of upper divider resistance is giving the extra voltage drop...the trouble is the FL6961 datasheet doesnt give the INV pin bias current, nor the tolerance on it.

Its sad because this is essential info....i presumed the bias current would be less than one microamp, otherwise surely they would have stated what it is.?

 

[D.A.(Tony)Stewart]

That's incorrect. the input bias current creates an input offset voltage across all resistors at this node. The shunt resistor to ground ~13k will consume most of the source or sink current and result in very little offset voltage. (~1% max)
You can drop this to 0.5% using 1/2 1M and 6.5k for 387V +/-4.5% or 405V max.

With 13k and +/-20uA typical bias current input offset is typically 260mV or +\-1% of 2.50V
Assume Vref internally is 2% error, total error +/- 5% with 13k and 4.5% with 6.5k
and choosing 0.1% 6.5k reduces the error budget to 3.6% or 401Vmax

 

[FvM]

With 13k and +/-20uA typical bias current input offset is typically 260mV or +\-1% of 2.50V

Actually 260 mV / 2.5V = > 10%.

Or simply 2MOhm * 20 µA = 40V, as previously calculated.

 

[treez]

So it looks to me that the potential divider, which is.......
upper resistance = 2.04 Megohms
Lower resistance = 13k

...is set up for 395V in the ideal world, but because of the bias current into the INV pin, it actually gives 418V output.

It just doesnt make sense that they haven't included the bias current in the datasheet, 418V output voltage is very different to 395V output.

 

[treez]

The UCC28180 PFC chip has just 250nA of input bias current into its output divider pin...so i very much doubt that the FL6961 chip has several microamps of bias current into its output divider pin....because if it did have that much leakage current into that pin, then it would be seriously poor in comparison to the UCC28180 and many others.

UCC28180 datasheet..page 6 gives the input bias current...
https://www.ti.com/lit/ds/symlink/ucc28180.pdf

 

[treez]

Hello, this question again involves the FL6961 PFC controller.....

Page 11 of the below App note on the FL6961 PFC controller shows its output voltage divider is an upper divider resistance of 1.17 megohms, and a lower divider resistor voltage of 6k8.
This corresponds to a PFC output voltage of 432V.

FL6961 PFC controller application note:
https://www.fairchildsemi.com/application-notes/AN/AN-9736.pdf

.....However, the text on page 3 of the same application note says its set up for 420V.

Do you know what’s going on here?.....the reason for the discrepancy?....also why there is no figure given in the FL6961 datasheet for leakage current into the INV pin? This is absolutely required information for any PFC controller.

FL6961 DATASHEET:
https://www.fairchildsemi.com/datasheets/FL/FL6961.pdf