Output of D flip flop with input and clk pin shorted

[Prameeth]

My query is when the clk pin is shorted to the input pin(Din) of d flip flop, will the output be zero or undefined? My understanding is when the clk is shorted to input as well, then there will be hold timing violation resulting in undefined output. Please correct me if I'm wrong.
Thank you

 

[danadakk]

Depends on how the architecture was done. But generally if you "float"
CMOS inputs you will get totally erratic behavior, everything from false
states to oscillation.

**broken link removed**

Above shows setup time violation, but hold is OK at 0 nS.


Regards, Dana.

 

[BradtheRad]

clk pin is shorted to the input pin(Din) of d flip flop

D FF inputs need to receive definite high or low value at startup and running. (As do all digital IC's).

Simply connecting inputs together is equivalent to leaving inputs floating which is not recommended. It can result in unpredictable behavior.

A D FF can receive any combination of hi or low voltage at input pins, once you achieve stable running.

 

[dick_freebird]

It depends which side of the setup time the
D transition (= CLK) lies. At tsetup>0 the output
will be 0 for a positive edge triggered 'flop (or
1 for a negative edge triggered.

For tsetup=0 the output will be undefined /
metastable.

Tsetup < 0 is abnormal in my experience.

 

[danadakk]

Decent description of D -

Positive, negative and zero setup time

Figure 4 shows a positive level-sensitive D-latch. As we know from the definition of setup time, setup time depends upon the relative arrival times of data and clock at input transmission gate (We have to ensure data has reached upto NodeD when clock reaches input transmission gate). Depending...

vlsiuniverse.blogspot.com

Regards, Dana.

 

[Prameeth]

Thanks a lot for the answers. I get the idea for the positive edge trig flop. But then, wouldn't there be only hold violation and not setup violation (assuming positive library setup and hold times of flop). Because anyway the clk which is the input is settled at Din(constant and not changing) at the active edge (rising edge in this case). But because the value at Din immediately changes after the positive edge, hold violation occurs. And hence output becomes unpredictable. Please correct me if I am wrong. Thank you.

 

[dick_freebird]

It all depends on those details. If you had a
transistor level DFF circuit netlist you could
simulate the real goings-on and understand.
Looking at "datasheet" numbers, sandbagged
as they tend to be, may be a source of some
confusion.

 

[BradtheRad]

Simulation of edge-triggered D flip-flop, with incoming pulses applied to both clock and D input simultaneously.

The result is erratic behavior, apparently because disallowed states occur. Flickering is seen among the branches connecting the NAND gates. (Green= high, gray= low). The left half of the circuit is stable only when inputs are low.

(Schematic is a spin-off of the model found in the Circuits menu of Falstad's animated simulator.)

 

[dick_freebird]

Structural veriloga has this problem if the gates
don't each have a finite delay. That's key to the
master-slave handoff. If everything has zero
delay then it all tries to happen at once (and
good luck with that - turns relay race into a
mosh pit).