output load explanation

[shivaram284]

what is output load and its relation with the input transition time and output load capacitence in design compiler?

 

[Prototyp_V1.0]

It depends on the output shape and the load characteristic.

 

[ic_qiand]

Hi, shivaram284

Normally, Transition Time = Load（C） * Drive （R）

 

[shivaram284]

Thank u........ and

what happens if output load is not mentioned to the tool?
what happens if transition time is not mentioned ?

 

[ic_qiand]

Actually, for each design(EDA), We often set the DRC rules, ie. max_transition max_fanout max_capacitance...

You can find "max transition" "max_fanout" ... in a library (.lib synopsys format)

If you dont set a "max transition" in constraint files, EDA tools will select the value of "max transition" as default.

I'll post a lib file here.

er ... the lib file is too large, i just post a paragraph of the lib file here.


/*** default specification ***/
input_threshold_pct_rise : 50.00;
output_threshold_pct_rise : 50.00;
input_threshold_pct_fall : 50.00;
output_threshold_pct_fall : 50.00;
slew_lower_threshold_pct_rise : 20.00;
slew_upper_threshold_pct_rise : 80.00;
slew_lower_threshold_pct_fall : 20.00;
slew_upper_threshold_pct_fall : 80.00;
slew_derate_from_library : 0.6;
default_max_transition : 5.0 ;
default_fanout_load : 0.6 ;
default_inout_pin_cap : 0.05 ;
default_input_pin_cap : 0.05 ;
default_output_pin_cap : 0.0 ;
default_cell_leakage_power : 0 ;
default_leakage_power_density : 0.0 ;
/*** default specification ***/
/* *** power tables are in energy units of 'pJ' *** */

/* *** fanouts are scaled to units of 20.000ff *** */

 

[yadavvlsi]

Cell delay is calculated from input transition and output load. The delay information is given in library in a tabular form along with input transition and output load. If this table is not available in library for a particular cell. Tool will not able to calculate the delay for that particular cell. Hence you will get an error.

 

[shivaram284]

thank u guys .... that helped a lot...