Output Impedance of 2 stage Opamp - please help!

[|IAngel|]

simulation output resistance

Ok - so I posted a short time ago about my amp having a supply of 500mV, - supply of 0V, an open loop gain of about 60dB, a phase margin of 45°, and a CMR from 40mV to 450mV (roughly, here) that was found by making the amp a UG buffer and watching where the output followed the input.

However, when put in CL mode as an inverting amplifier, it fails. It was suggested to test my output impedance.

Here's where I need help: I tested the output impedance by leaving the Vdd, Vss, +ve and -ve inputs floating. I applied a test voltage of 1V at the output and measured the current going in. Dividing the test voltage by the current the simulator gave me, I got a resistance of about 125x10^12 Ohms (125 TOhms)... That's insane! Is that why my circuit is failing as a closed loop device? It seems to me that this would limit the amount of input to the output, and therefore allow the diff. pair to take care of the feedback - which would make me think that would work... What do you all think?

edit: I've now also tried grounding the Vdd, Vss, +ve and -ve inputs. applied a test voltage of 1V at the output and measured the current going in. Dividing the test voltage by the current the simulator gave me, I got a resistance of about 1.2k Ohms (1.2^10^3 Ohms). This seems quite low.

Which of the simulations should I trust for output impedance? Do I ground all the terminals of the circuit to test it, or do I leave them all floating to test it? Is there a better way to test output Impedance of a circuit with Cadence?

Should I try to lower the output impedance? And if so/not could you explain why and give suggestions?

Thanks! I appreciate the help!

 

[aryajur]

output impedance opamp

Are you doing this with an actual device or in simulation. Either way if you disconnect all the supplies and then calculate the output impedance you will definitely get such a high resistance since all the MOS or BJT are cut off. Output impedance in this case means the small signal output impedance for which you only have to zero out the small signals and send in a small signal variation in the output and measure the small signal current going in the output and then calculate the output impedance.
When you say the opamp does not work in Closed loop config, what exactly goes wrong? YOu are not getting the expected gain or the output voltage? Maybe the opamp cannot source high enough current to create the appropriate voltage output. Try increasing the Resistor sizes keeping the resistor ratio to be the same for the same gain.

 

[|IAngel|]

how to check output impedance

Thank you! I will try that.

I tested it again with the bias connected and found my output impedance to be 800kOhms. I have a 500mV source at the output and it draws about 641nA.

I'll make the transistors much wider and try again. Perhaps there is a current generation issue as I am trying to minimize current with this amp. Why would a low output current cause this to fail?

It isn't working beacause to test the amp in closed loop mode, I put a 2kOhm feedback resistor and a 1kOhm resistor from the input small signal to the -ve terminal. This should give me an inverting amplifier with a gain of 2. Instead, I get a gain of below 1, and changing the resistor values doesn't change anything. Even if I change the ratio, it still doesn't make any difference.

Overall, I need to use this amplifier to take a signal around that varies linearly about 20mV in magnitude with a 250mV offset. I want to remove the offset and amplify it to be a 200-300mV signal from around 0V-200/300mV. I was going to use a difference amplifier to do this (unless people have a better suggestion). I tried the simple inverting amplifier test to see if I could get the amp working in general, but it fails as mentioned in closed loop testing.

This is a simulation as this amp is supposed to be only one block of a circuit I am working on.

Added after 9 minutes:

aryajur:

I tried increasing the resistors from 1k/2k to 1G/2G.

The output small signal was a constant 0.9 gain with every ratio (with 0DC input bias). If the bias was increased to set the AC signal to a DC level in the CMR (say 200mV), the ac signal was way more compressed and the gain was always around 0.25. So it is possible the current isn't the problem, no?

Do you have any other suggestions?

Thanks for your help and time!
Scott

 

[aryajur]

output impedance test

A output voltage of the unloaded inverting configuration is V- plus output opamp current times the feedback resistor. Your feedback resistor is 2K so if suppose the maximum you can source from your opamp is 100uA then the maximum output voltage that the opamp can provide is sound 200mV.
Also if your output resistance is 800K then it makes sense because with such a high output impedance and low output current all voltage will be dropped in the output impedance itself. If you plan to use a 2K resistor as the total load resistance to the opamp then the output resistance should be I think max 200 ohms to have good operation.

 

[|IAngel|]

small signal output impedance

Oh Isee, thank you so much! I'll have to clicky a helpful button there

One last question then, for my simulation to make sure I'm calculating my output impedance correctly, I have my FETs biased at Vdd (500mV), Vss (0V), inputs are at 0V, and I put a DC 500mV signal into the output and divided by the simulated current into the output. Is this right? Or should I put 0V DC at the output and a small signal (say 1uV sine wave, as I was using to test my ss input) at the output and use that to calculate it. That might be why I'm getting such a high output impedance.

Thank you again for your time!

 

[aryajur]

Its strange that when you increase the input bias in the Common Mode range your gain decreases ! The current sourcing doesn't seem to be the problem I guess. How are you testing this configuration? What is your input? How did you test the 60dB gain initially? I would have to know more to understand whats going on.

 

[|IAngel|]

Having applied a 1uV test sine wave to the output, the AC current in was 16.4pA. This gave an output impedance of 60.4kOhms.

I suppose I have to increase the transistor sizes of the output stage to decrease this, huh?

 

[aryajur]

For the output impedance calculation your input should be biased inside the common mode range. Also the output small signal should be applied at a Output Common Mode level.

Would be nice if you click the helped me button

 

[|IAngel|]

Ok - to test I have a 1uV sine wave. I put this in the +ve terminal and the same signal into the -ve terminal 180° out of phase. To find my gain and CMR, I swept the input DC bias (the DC level these small signals are inputted on) and found the simulated open loop gain. This gave me a gain of about 40dB between 0mV bias - 80mV bias and again from 450mV-500mV bias. From 80mV - 450mV the gain went from about 40dB to 60dB open loop gain. I found the phase margin to be 45° - so it should be stable. I connected the negative terminal to the output and found the CMR to be 80-450mV (roughly), as the output voltage was at unity gain with the input voltage at these points.

So it seems to work open loop, and even as a unity gain buffer. When I add resistors though, it craps out. And yes, the gain (ss gain) seemed to go from about 0.9 at no bias (outside CMR) and drop across the rest of the bias points...

 

[aryajur]

Maybe what you can try next is to test it in open loop with a resistor load and see how it goes...

 

[|IAngel|]

Thanks! I will try that next!
I'll post how it goes! And I'll try a common mode output level of bias and re-try the output impedance calculations as well! thank you!

 

[Alles Gute]

hi, |IAngel|
I think aryajur's reply hit your point. You can find simulation of opamp in Allen's book, second edition section 6.6.
BTW:you said your supply is 500mV, quit low. What process do you use?

 

[|IAngel|]

Thanks, Alles!

I'm using a 0.13um and 90nm process (IBM and STC). I'll look in that book for simulation help - to be honest I haven't really looked at that book in a long time! Although both of these processes have 0 threshold devices to allow simple circuits to run in saturation at 500mV, I am running them in the sub-threshold region to try and optimize the power consumption of the circuit.

Added after 15 minutes:

Ok - so I tried it in open loop with an output resistance. You were right on. It died. Any resistance kills it, so teh output impedance of my circuit must be WAY too high, huh?

I'll see if I can lower it now...

Thanks!