Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Output delay for hold, positive and negative

Status
Not open for further replies.

fragnen

Full Member level 4
Full Member level 4
Joined
Apr 3, 2019
Messages
211
Helped
0
Reputation
0
Reaction score
1
Trophy points
18
Activity points
1,487
Is -ve output delay for hold better than a positive out delay for hold? Which one is better between the two output delays?

set_output_delay -1.5 -hold -clock clk1 out_a
sett_out_put_delay 1.5 -hold -clock clk1 out_a

In the first case a -ve hold value defined and in the second case a +ve hold value defined for the same output out_a with respect to same clock clk1.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top