Oscillator with the attribute of PLL

Design a oscillator with 1MegHz typical frequency, and external synchronization frequency from 500KHz to 1.5MegHz.

Use PLL, need a big capacitor for LPF. And still need a lot of chip area even using capacitance multiplier.

I want other methods to implement the frequency spec. Please help me.

Thanks!
Edwin.

if you just want to implement a doubler , you can use an xor in a feedback loop like a DLL which would be a decent implementation of the system, though would not be as rugged as a pll, but this still saves you a lot of area.


amarnath

Hi amarnath,

I didn't understand your method. Use it how to implement the frequency spec.

Thanks!
Edwin.

hi, tell me exactly what is the output frequency you want to acheive, is it only one frequency or a no of frequencies. If you just want to output a frequency say 2x from an input frequency of x , then you can use a frequency doubler instead of a pll. The implementation is as follows:



one input is given directly to the xor gate , the other input is given in a delayed manner through a series of inverters. Now once this is done , sense the output of the xor gate through an rc filter. When you double the frequency you would definitely want an equal duty cycle at the output. So a 50% duty cycle square wave would generate a voltage of vdd/2 across the capacitor, so use this property and compare this voltage with a reference signal of vdd/2. Now both the reference voltage(vdd/2) and the output of the rc filter are input to an error amplifier, now use the output of this opamp to modulate the current in the delay stages.Hope this is clear, any doubt let me know.


amarnath

amarnath, your description is quite clear. Thanks!
-----------------------------------------
free-running typical frequency: 1MegHz
external synchronized frequency: 500KHz to 1.5MegHz
In my recent project i use a PLL with a external PIN for LPF(need big capacitance). Now the PIN was effaced.
So i need push the LPF into the chip (waste much chip area), or use other method.

B/R
Edwin.

since your input varies from 0.5 to 1.5M, just use the method suggested above in my previous post and then use some digital logic for programming the current for different input frequencies , since the doubler bias current needs to be more for doubling higher frequencies. You can use some architecture like swithching a series of current sources in a progressive manner with increasing input frequency(use a decoder to decode your input frequency and then give its output to the current sources which are used the change the currents in the delay elements. If in all cases you need an output frequency of 1M, then divide the output using a divider again.


amarnath