Oscillator for EP1C3

I'm building my first FPGA circuit using an Altera EP1C3 and had a few questions regarding the oscillator:

1) I assume any oscillator frequency up to the rated max (200-something MHz) will work? I'm considering either 50- or 100 MHz (cost reasons and application doesn't need more)

2) The FPGA has two clock inputs. Can it be driven off an oscillator with one a single output (4-pin variety) or is a differential output better/required (6-pin ones)?

3) I heard that sometimes one requires a resistor (if the oscillator is far from the fpga on the board). What's the correct value for this resistor? Should it be on the first/second output or both outputs?

4) How to I work out what capacitor values I ideally need on the oscillator output lines?

Any advice would be great - thanks!

1) Any frequency is fine
2) You can use MANY inputs as clock inputs, not just two. Don't confuse "clock inputs" with the fact that there are 2 PLLs (which you may or may not need)
3) Put the oscillator near the FPGA. The resistor is to suppress reflections. Put the oscillator near the FPGA.
4) You don't want ANY capacitors on the oscillator output!

barry said:

3) Put the oscillator near the FPGA. The resistor is to suppress reflections. Put the oscillator near the FPGA.

Click to expand...

Are we talking series or parallel resistance?

A series resistor placed near the oscillator output should have a value such that the combined oscillator output impedance and the resistor is equal to the board trace impedance (nominally 50 ohms), but this only makes sense if you place your oscillator far away from the FPGA. If the oscillator is very close to the FPGA then there isn't any need for a resistor as there won't be any problems with reflections as such short traces won't behave like a transmission line.

If you want a cleaner clock then use an LVDS clock oscillator. e.g. SiT9121, then you'll need to have a 100 ohm termination resistor between the differential pair as close to the FPGA clock input pins (or enable the internal termination if the FPGA has that). SiTime also has a lot of single ended MEMs parts that are less than $2 USD.

1) I assume any oscillator frequency up to the rated max (200-something MHz) will work? I'm considering either 50- or 100 MHz (cost reasons and application doesn't need more)

Click to expand...

The choice of clock should be based upon the fastest signal you intend to sample.
For example - If your fastest signal is 1MHz - then a 50MHz is a good choice. If your fastest signal is 40MHz - then perhaps it would be better to use a faster clock. Anyways, if you use a common footprint for your oscillator, you can switch between components. It is however important to connect your clock signal to a dedicated FPGA clock pin. One thing to consider with FPGAs - the maximum frequency is VERY dependent on the logic design! For example - a device can be rated by the manufacturer for 300MHz and at the same time the design implemented on it will have a maximum usable frequency of not more then 10 MHz.

2) The FPGA has two clock inputs. Can it be driven off an oscillator with one a single output (4-pin variety) or is a differential output better/required (6-pin ones)?

Click to expand...

At low speeds / short trace length a differential clock isn't necessary. Use a single ended clock signal ("4 pin variety" as you call it)

3) I heard that sometimes one requires a resistor (if the oscillator is far from the fpga on the board). What's the correct value for this resistor? Should it be on the first/second output or both outputs?
4) How to I work out what capacitor values I ideally need on the oscillator output lines?

Click to expand...

If you use a series termination, the values of the resistor should be the impedance of the Tx line (usually 50 Ohm) minus the output impedance of the driving buffer. Given very short trace length, it's possible not to use a termination resistor. I still advice you however to do so. the resistor's pad can serve as a useful test point for the clock signal. Suppose the output impedance of the oscillator is 10 Ohm and the impedance of the PCB clock trace is 50 Ohm - then your series termination resistor will have to be 50 - 10 = 40 Ohm.

Many thanks for all the helpful answers.
I guess I'll use a single-ended output with a termination resistor.
So I just connect this to CLK0 input pin of the fpga and leave the CLK pin NC?

What's the full product number of the FPGA you're using?

shaiko said:

What's the full product number of the FPGA you're using?

Click to expand...

ep1c3t100c8n

I guess I'll use a single-ended output with a termination resistor.
So I just connect this to CLK0 input pin of the fpga and leave the CLK pin NC?

Click to expand...

Using a single ended crystal oscillator is in fact the standard configuration used in most FPGA designs.

There a two basic scenarios:
- PLL generated design clocks. EP1C3 has only one PLL, thus connecting a single clock input should be sufficient. There's no advantage in using a high frequency clock oscillator, a value between 16 and 50 MHz is usually appropriate. Check that all required frequencies can be generated with the selected oscillator frequency.

- Not using PLL. You may have problems with stable PLL operation in a "noisy" PCB layout. Also requirement of low jitter clocks (e.g. for digital signal processing) may be a reason not to use the internal PLL. For high oscillator frequencies > 100 MHz, differential (LVDS) connection is preferred in this case.

Unused FPGA clock inputs should be connected to ground.

Unused FPGA clock inputs should be connected to ground.

Click to expand...

depletionmode,
What FvM says is correct. However, because you don't have a lot of FPGA / board design experience I suggest not to short the unused pins directly to ground or VCC - instead do it through a resistor (~10KOhm).

This will enable easy post manufacturing repairs if required.
Call it "debugging oriented design"...

shaiko said:

depletionmode,
What FvM says is correct. However, because you don't have a lot of FPGA / board design experience I suggest not to short the unused pins directly to ground or VCC - instead do it through a resistor (~10KOhm).

This will enable easy post manufacturing repairs if required.
Call it "debugging oriented design"...

Click to expand...

Actually, you can specify unused inputs to have weak pullups internally (among other options). To add a bunch of external resistors is not necessary and will just make routing the pcb harder.

To add a bunch of external resistors is not necessary and will just make routing the pcb harder.

Click to expand...

I don't advice it as a general practice for every design.
In this case however, because it's the first time the OP designs a board with an FPGA on it - I think it's a good idea (if routing & board space allow that).
It'll enable much simpler repairs in case an important pin is (mistakingly) left unconnected.

Thanks for all the help and advice.
I've pulled together a basic schematic together for the fpga board. Does this look right (my first attempt)?
Also first time using KiCad (usually I use Eagle) so sorry if things are weird...

View attachment cpu.pdf

A few remarks
- Insufficient bypass capacitors for FPGA supply voltages.
- VCCA_PLL should have a RC or LC filter if the PLL is used.
- Signal CE to AS programming header incorrectly connected
- No need for jumper at MSEL0 unless you plan to use PS configuration scheme.
- JTAG header has no Altera standard pinning
- Instead of AS programming header, configuration flash can be programmed by JTAG indirect method through JTAG header.

1.I usually connect the FPGA pins that lead to exteral connectors with buffers. If not a buffer than at least a series resistor to limit the current and provide some means of termination.

2. I strongly suggest you use decoupling capacitors on the vdd of the oscillator, FPGA memory and of course the FPGAs power nets.

3. With USB being your power source, It might be a good idea to use protection diodes between the connector and LDOs. Also, because you're using USB (which is hot swappable) avoid using a large inductor on the LDOs - (reference designator: L?).

@FvM
Would a ferride bead on the VCCA_PLL be sufficient?
I guess I'd prefer to do away with the download cable header. The jtag indirect method doesn't require any special configuration on the fpga does it? It should work out-of-the-box with flash loader?

@shaiko
I'll bang some resistors ont he outputs; although i thought there were internal pull-ups?
The L? on the LDO input is a ferride bead... is this wrong (I've been using this before on some of my oither boards )?

I will also decouple the power nets as you both suggest - and the osc VDD. thanks!

I'll bang some resistors ont he outputs; although i thought there were internal pull-ups?
The L? on the LDO input is a ferride bead... is this wrong (I've been using this before on some of my oither boards )?

Click to expand...

The internals are parallel - I suggested adding series resistors...


A low inductance ferrite is fine...

I suggest you control impedance by design for 10% max tolerance for source, transmission and termination values.

ALCV2 family CMOS has 25 Ohm drivers, so 25 Ohm series Rs, is used for PCBA stripline or microstrip of 50 Ohms per line.

Thus termination would be differential 100 ohm or for single ended, 50 ohm terminated to Vcc/2 or equiv.

I havent added the drivers yet but I've updated the power nets. Have I gone overkill?? (schematic attached).

I thought the ferrite beads should be high impedance (low-Q) for circuit isolation?

The bypassing looks O.K. now. Regarding drivers, I'm not sure if they are needed or even helpful for your application. There's also no point of impedance matching with ribbon cable connectors placed near the FPGA. The best thing probably is that drivers add some protection to FPGA I/Os. But you need to fix the data direction in advance.

Everything depends on the intended FPGA usage, speed and I/O-standard of external signals and electrical parameters of the connected circuit. You can refer to the design of recent FPGA evaluation boards (many user manuals and schematics downloadable at Altera and Terasic).

Some evaluation boards have schottky clamp diodes and current limiting resistors for external interface pins.

I've decided to leave off the drivers for now to leave my first attempt at a board generic. It has to externally interface with a bunch of other boards at the moment. The final design I'll put everything on one board and have more control.

Many thanks for all your help everyone!