johnnyarancia
Newbie level 2
Hello everyone, this is a beginner question but so far I could not figure it out. I searched through example projects, official help and the web for several days to no avail.
I need to add a PCIe interface to Cyclone IV GX FPGA, for starters i want to connect just four transceiver pins (one lane, txp-txn-rxp-rxn). There is no predefined interface, so i started with pcie_x1_s2gx which is made for Stratix II GX. I deleted all pins except the four I wa interested in. It still connects to a Stratix II GX FPGA without any problem.
Then I edit the interface rules and change target family to Cyclone IV GX, leaving everything else the same (IO standard PCML15, target pin function High Speed (GXB)).
Now i get an error messsage: The high-speed serial IO pins in the part model should have a group constraint of pll_compensated_path or pll_non_compensated_path.
When I add this constraint, new error appears: Group Lane0 with pll_compensated_path constraint in part part should contain a minimum of 1 input clock pins or 1 PLL output clock pins.
Adding a clock to this group does not help either, because then it somehow tries to connect all the signals to one I/O bank which obviously fails.
:bang:I am out of ideas now. In this case the FPGA has only 169 pins, which is doable wihout the help of FSP, but for future I would like to know how is it done the proper way.
Thank you very much for any tip.
I need to add a PCIe interface to Cyclone IV GX FPGA, for starters i want to connect just four transceiver pins (one lane, txp-txn-rxp-rxn). There is no predefined interface, so i started with pcie_x1_s2gx which is made for Stratix II GX. I deleted all pins except the four I wa interested in. It still connects to a Stratix II GX FPGA without any problem.
Then I edit the interface rules and change target family to Cyclone IV GX, leaving everything else the same (IO standard PCML15, target pin function High Speed (GXB)).
Now i get an error messsage: The high-speed serial IO pins in the part model should have a group constraint of pll_compensated_path or pll_non_compensated_path.
When I add this constraint, new error appears: Group Lane0 with pll_compensated_path constraint in part part should contain a minimum of 1 input clock pins or 1 PLL output clock pins.
Adding a clock to this group does not help either, because then it somehow tries to connect all the signals to one I/O bank which obviously fails.
:bang:I am out of ideas now. In this case the FPGA has only 169 pins, which is doable wihout the help of FSP, but for future I would like to know how is it done the proper way.
Thank you very much for any tip.