or in Verilog for coding flipflop

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sun_ray

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What is this or when we use this or as shown below in Verilog? Verilog has a || operator for OR.

always @ (posedge clock or negedge reset)
 

In Verilog "or" is not an operator; It is an operand namely Identifier, Please refer to the below links **broken link removed** , **broken link removed**
 

Both the or operator and comma , operator mean either event. It the same as writing @(posedge clock, negedge reset), which can be read as "wait for either a positive edge of clock, or a negative edge of reset". You cannot logically OR these two events together.
Note that @(A || B) is very different from @(A or B). The former means "wait for the result of the expression A||B to change", whereas the latter means "wait for a change on either A or B".
 
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    no_mad

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I agree with the reply.......
 


Do you want to mean that the following tow conditions are equivalent?

@(posedge clock, negedge reset)

@(posedge clock or negedge reset)
 

It's all about reading
 

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