In Verilog "or" is not an operator; It is an operand namely Identifier, Please refer to the below links **broken link removed** , **broken link removed**
Both the or operator and comma , operator mean either event. It the same as writing @(posedge clock, negedge reset), which can be read as "wait for either a positive edge of clock, or a negative edge of reset". You cannot logically OR these two events together.
Note that @(A || B) is very different from @(A or B). The former means "wait for the result of the expression A||B to change", whereas the latter means "wait for a change on either A or B".
Both the or operator and comma , operator mean either event. It the same as writing @(posedge clock, negedge reset), which can be read as "wait for either a positive edge of clock, or a negative edge of reset". You cannot logically OR these two events together.
Note that @(A || B) is very different from @(A or B). The former means "wait for the result of the expression A||B to change", whereas the latter means "wait for a change on either A or B".
Both the or operator and comma , operator mean either event. It the same as writing @(posedge clock, negedge reset), which can be read as "wait for either a positive edge of clock, or a negative edge of reset". You cannot logically OR these two events together.
Note that @(A || B) is very different from @(A or B). The former means "wait for the result of the expression A||B to change", whereas the latter means "wait for a change on either A or B".
The logical OR of any number of events can be expressed so that the occurrence of any one of the events
triggers the execution of the procedural statement that follows it. The keyword or or a comma character (,)
is used as an event logical OR operator. A combination of these can be used in the same event expression.
Comma-separated sensitivity lists shall be synonymous to or-separated sensitivity lists.