Opto-coupler pole in SMPS feedback

[eem2am]

optocoupler application note

Hello,

On page 12, 13 and 14 of AN1059 application note they do the feedback compensation for the L6561 flyback power factor corrector circuit.

****AN1059 Flyback PFC application note.
https://www.st.com/stonline/products/literature/an/5956.pdf


However, considering the equation at the bottom of page 14 (H(s)), or any other transfer functions listed, -None of them include the effect of the opto-coupler pole.

Also, the diagram at figure 15, (top of page 15) does not show the opto-coupler pole equivalent capcitor which should appear accross the Collector-Emitter of the opto transistor.




In relation to this, -pease may I quote from Basso’s book, page 322………

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“Compensating the power supply without keeping in mind the opto-coupler pole position is useless. Always measure or compute the pole position and include it in the loop design process to avoid last-minute bad surprises”
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The AN1059 application note clearly has taken no account of the opto-coupler pole.

Do you know how this can be so?

Thankyou very much for reading.

 

[FvM]

optocoupler application + smps

I think, you gave the answer yourself in another discussion, considering the rather small bandwidth of PFC voltage control loop.

 

[eem2am]

flyback voltage feedback opto

Thankyou FvM,

I appreciate that the opto-coupler pole will simply make the loop bandwidth smaller and so the power factor will still be good......but the bandwidth will then be too small, and the output voltage regulation will be very bad.

and as you know, the idea is to get the best possible output voltage regulation whilst passing the regulatory laws on power factor.

Since the opto-coupler pole has not been accounted for, the output voltage regulation will suffer unnecessarily.

I am wondering why they have neglected this opto-coupler pole?

 

[FvM]

692 optocoupler

I don't understand your considerations at all. Assume a very low OC equivalent corner frequeny of 1 kHz (10 kHz or above would be a better guess). PFC voltage control loop may have e.g. 10 Hz loop bandwidth. At this frequency, the phase lag caused by the OC pole is about 0.6 degrees (arctan(0.01)).