Optimum amplitude of the clock for switched capacitors

[cjupiter]

clock voltages

When applying clocks to switched capacitor circuits, what would be the optimum amplitude of the clock. ie. should it be equal, slightly greater, or much greater than threshold voltage of mosfet?

 

[cetc1525]

clock voltages

I think the noise and it's rate is first thing.

 

[anadigi]

Re: clock voltages

Obviously the amplitude shd be very higher than threshold voltage..
8O

 

[devrimaksin]

clock voltages

The amplitude of course should be very high
than threshol voltage,
you want to use those transistor as a switch
so their equivalent on resistance should be
as small as possible
Ron=1/beta/(vgs-Vt)
so you increase Vgs, Ron decreases

 

[huanchou]

Re: clock voltages

In my view, the voltage should be as high as possible ( voltage rail),
the SNR will be better.

 

[borodenkov]

clock voltages

The higher the better.. Normally power supply voltage is used. However sometimes clock boosting (applying higher voltage than Vdd) is used to increase switch linearity. However that will introduce the problem of gate oxide reliability.

 

[terryssw]

Re: clock voltages

In terms of gate oxide reliablity, I have some doubt (Actually I am not quite sure and I want to get some comments from all of you): If I use bootstrap circuit to ensure the gate-source voltage to equal constantly VDD, then at any time the maximum voltage across the oxide is equal to VDD, and this should not create oxide reliablity problem. But how about the gate bulk voltage? If working in this way the gate bulk voltage will exceed VDD, am I right? will it contribute to gate-oxide problems?

 

[borodenkov]

clock voltages

As far as I understand it..

The original boostrap circuit produces clock voltages that are higher than Vdd (e.g. voltage pumps described in Baker/Li/Boyce CMOS book). The level of the clock on voltage is constant, so Vgs is again signal dependent, although higher than when using normal clock. This approach may cause problems with gate oxide reliabilty.

Modified circuit as described in "A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter" by Abo & Gray provides constant Vgs equal to Vdd (so that Vg is signal dependent). They write that such a circuit will not reduce oxide reliability, so it seems that if Vgb will exceed Vdd, it will not cause problems with reliability.

Can someone explain it in the terms of device physics??